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experimental/unstable t480 thunderbolt support

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Signed-off-by: Leah Rowe <leah@libreboot.org>
This commit is contained in:
Leah Rowe
2024-12-10 23:35:47 +00:00
parent b910424b5d
commit 3881160b86
6 changed files with 409 additions and 4 deletions
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265
config/coreboot/next/patches/0010-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch Normal file
View File

@@ -0,0 +1,265 @@
From 0db8646d574c07c40793bad5e5ab768da6161628 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Thu, 5 Dec 2024 20:35:23 +0000
Subject: [PATCH 1/2] drivers/intel/dtbt: Add discrete Thunderbolt driver
Add a new driver for discrete Thunderbolt controllers. This allows using
e.g. Maple Ridge devices on Raptor Point PCH.
Ref: Titan Ridge BIOS Implementation Guide v1.4
Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472)
Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
src/drivers/intel/dtbt/Kconfig | 4 +
src/drivers/intel/dtbt/Makefile.mk | 3 +
src/drivers/intel/dtbt/chip.h | 8 ++
src/drivers/intel/dtbt/dtbt.c | 199 +++++++++++++++++++++++++++++
4 files changed, 214 insertions(+)
create mode 100644 src/drivers/intel/dtbt/Kconfig
create mode 100644 src/drivers/intel/dtbt/Makefile.mk
create mode 100644 src/drivers/intel/dtbt/chip.h
create mode 100644 src/drivers/intel/dtbt/dtbt.c
diff --git a/src/drivers/intel/dtbt/Kconfig b/src/drivers/intel/dtbt/Kconfig
new file mode 100644
index 0000000000..5c03a97db9
--- /dev/null
+++ b/src/drivers/intel/dtbt/Kconfig
@@ -0,0 +1,4 @@
+config DRIVERS_INTEL_DTBT
+ def_bool n
+ help
+ Support for discrete Thunderbolt controllers
diff --git a/src/drivers/intel/dtbt/Makefile.mk b/src/drivers/intel/dtbt/Makefile.mk
new file mode 100644
index 0000000000..1b5252dda0
--- /dev/null
+++ b/src/drivers/intel/dtbt/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c
diff --git a/src/drivers/intel/dtbt/chip.h b/src/drivers/intel/dtbt/chip.h
new file mode 100644
index 0000000000..2b1dfa70a5
--- /dev/null
+++ b/src/drivers/intel/dtbt/chip.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
+#define _DRIVERS_INTEL_DTBT_CHIP_H_
+
+struct drivers_intel_dtbt_config {};
+
+#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */
diff --git a/src/drivers/intel/dtbt/dtbt.c b/src/drivers/intel/dtbt/dtbt.c
new file mode 100644
index 0000000000..a54f0e213d
--- /dev/null
+++ b/src/drivers/intel/dtbt/dtbt.c
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <acpi/acpigen.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+#include <timer.h>
+
+#define PCIE2TBT 0x54C
+#define PCIE2TBT_VALID BIT(0)
+#define PCIE2TBT_GO2SX 2
+#define PCIE2TBT_GO2SX_NO_WAKE 3
+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED 4
+#define PCIE2TBT_OS_UP 6
+#define PCIE2TBT_SET_SECURITY_LEVEL 8
+#define PCIE2TBT_GET_SECURITY_LEVEL 9
+#define PCIE2TBT_BOOT_ON 24
+#define PCIE2TBT_USB_ON 25
+#define PCIE2TBT_GET_ENUMERATION_METHOD 26
+#define PCIE2TBT_SET_ENUMERATION_METHOD 27
+#define PCIE2TBT_POWER_CYCLE 28
+#define PCIE2TBT_SX_START 29
+#define PCIE2TBT_ACL_BOOT 30
+#define PCIE2TBT_CONNECT_TOPOLOGY 31
+
+#define TBT2PCIE 0x548
+#define TBT2PCIE_DONE BIT(0)
+
+// Default timeout for mailbox commands unless otherwise specified.
+#define TIMEOUT_MS 1000
+// Default timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command.
+#define GO2SX_TIMEOUT_MS 600
+
+static void dtbt_cmd(struct device *dev, u32 command, u32 data, u32 timeout)
+{
+ u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID;
+ u32 status;
+
+ printk(BIOS_DEBUG, "dTBT send command %08x\n", command);
+ pci_write_config32(dev, PCIE2TBT, reg);
+
+ if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) {
+ printk(BIOS_ERR, "dTBT command %08x send timeout %08x\n", command, status);
+ }
+
+ pci_write_config32(dev, PCIE2TBT, 0);
+ if (!wait_ms(timeout, !(pci_read_config32(dev, TBT2PCIE) & TBT2PCIE_DONE))) {
+ printk(BIOS_ERR, "dTBT command %08x clear timeout\n", command);
+ }
+}
+
+static void dtbt_write_dsd(void)
+{
+ struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+
+ acpi_device_add_hotplug_support_in_d3(dsd);
+ acpi_device_add_external_facing_port(dsd);
+ acpi_dp_write(dsd);
+}
+
+static void dtbt_write_opregion(const struct bus *bus)
+{
+ uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS
+ + (((uintptr_t)(bus->secondary)) << 20);
+ const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000);
+ const struct fieldlist fieldlist[] = {
+ FIELDLIST_OFFSET(TBT2PCIE),
+ FIELDLIST_NAMESTR("TB2P", 32),
+ FIELDLIST_OFFSET(PCIE2TBT),
+ FIELDLIST_NAMESTR("P2TB", 32),
+ };
+
+ acpigen_write_opregion(&opregion);
+ acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
+ FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
+}
+
+static void dtbt_fill_ssdt(const struct device *dev)
+{
+ struct bus *bus;
+ struct device *parent;
+ const char *parent_scope;
+ const char *dev_name = acpi_device_name(dev);
+
+ bus = dev->upstream;
+ if (!bus) {
+ printk(BIOS_ERR, "dTBT bus invalid\n");
+ return;
+ }
+
+ parent = bus->dev;
+ if (!parent || parent->path.type != DEVICE_PATH_PCI) {
+ printk(BIOS_ERR, "dTBT parent invalid\n");
+ return;
+ }
+
+ parent_scope = acpi_device_path(parent);
+ if (!parent_scope) {
+ printk(BIOS_ERR, "dTBT parent scope not valid\n");
+ return;
+ }
+
+ /* Scope */
+ acpigen_write_scope(parent_scope);
+ dtbt_write_dsd();
+
+ /* Device */
+ acpigen_write_device(dev_name);
+ acpigen_write_name_integer("_ADR", 0);
+ dtbt_write_opregion(bus);
+
+ /* Method */
+ acpigen_write_method_serialized("PTS", 0);
+
+ acpigen_write_debug_string("dTBT prepare to sleep");
+ acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB");
+ acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1);
+
+ acpigen_write_debug_namestr("TB2P");
+ acpigen_write_store_int_to_namestr(0, "P2TB");
+ acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0);
+ acpigen_write_debug_namestr("TB2P");
+
+ acpigen_write_method_end();
+ acpigen_write_device_end();
+ acpigen_write_scope_end();
+
+ printk(BIOS_DEBUG, "dTBT fill SSDT\n");
+ printk(BIOS_DEBUG, " Dev %s\n", dev_path(dev));
+ //printk(BIOS_DEBUG, " Bus %s\n", bus_path(bus));
+ printk(BIOS_DEBUG, " Parent %s\n", dev_path(parent));
+ printk(BIOS_DEBUG, " Scope %s\n", parent_scope);
+ printk(BIOS_DEBUG, " Device %s\n", dev_name);
+
+ // \.TBTS Method
+ acpigen_write_scope("\\");
+ acpigen_write_method("TBTS", 0);
+ acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
+ acpigen_write_method_end();
+ acpigen_write_scope_end();
+}
+
+static const char *dtbt_acpi_name(const struct device *dev)
+{
+ return "DTBT";
+}
+
+static struct pci_operations dtbt_device_ops_pci = {
+ .set_subsystem = 0,
+};
+
+static struct device_operations dtbt_device_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .acpi_fill_ssdt = dtbt_fill_ssdt,
+ .acpi_name = dtbt_acpi_name,
+ .scan_bus = pciexp_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &dtbt_device_ops_pci,
+};
+
+static void dtbt_enable(struct device *dev)
+{
+ if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+ return;
+
+ if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL)
+ return;
+
+ // TODO: check device ID
+
+ dev->ops = &dtbt_device_ops;
+
+ printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev));
+
+ // XXX: Recommendation is to set SL1 ("User Authorization")
+ printk(BIOS_DEBUG, "dTBT set security level SL0\n");
+ dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, 0, TIMEOUT_MS);
+ // XXX: Must verify change or rollback all controllers
+
+ if (acpi_is_wakeup_s3()) {
+ printk(BIOS_DEBUG, "dTBT SX exit\n");
+ dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, TIMEOUT_MS);
+ // TODO: "wait for fast link bring-up" loop (timeout: 5s)
+ } else {
+ printk(BIOS_DEBUG, "dTBT boot on\n");
+ dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, TIMEOUT_MS);
+ }
+}
+
+struct chip_operations drivers_intel_dtbt_ops = {
+ .name = "Intel Discrete Thunderbolt",
+ .enable_dev = dtbt_enable,
+};
--
2.39.5

136
config/coreboot/next/patches/0011-thunderbolt-fix-ish.patch Normal file
View File

@@ -0,0 +1,136 @@
From dbc0c75d666045eb0716e2ad0656a29b562c8f66 Mon Sep 17 00:00:00 2001
From: Mate Kukri <km@mkukri.xyz>
Date: Thu, 5 Dec 2024 20:42:40 +0000
Subject: [PATCH 2/2] thunderbolt fix-ish
it shows up, but resume is no dice.
Change-Id: I2d91a1d290b35e7ea3a1193b4be7b4ba936e4a15
---
src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 1 +
src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 13 +++++++++++++
.../lenovo/sklkbl_thinkpad/variants/t480/gpio.c | 8 ++++----
.../sklkbl_thinkpad/variants/t480/overridetree.cb | 4 ++++
.../lenovo/sklkbl_thinkpad/variants/t480s/gpio.c | 8 ++++----
.../sklkbl_thinkpad/variants/t480s/overridetree.cb | 4 ++++
6 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
index 21076315ab..0766c03716 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -19,6 +19,7 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
+ select DRIVERS_INTEL_DTBT
config BOARD_LENOVO_E460
bool
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
index 237500775f..849540d32d 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
@@ -35,4 +35,17 @@ DefinitionBlock(
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Scope (\_SB)
+ {
+ External (\TBTS, MethodObj)
+
+ Method (MPTS, 1, Serialized)
+ {
+ If (CondRefOf (\TBTS))
+ {
+ \TBTS()
+ }
+ }
+ }
}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
index f7c29e1f39..edfa09fbb7 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C18, NONE),
PAD_NC(GPP_C19, NONE),
PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
+ PAD_CFG_GPO(GPP_C21, 1, DEEP), /* TBT_FORCE_PWR */
PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_G1, NONE),
PAD_NC(GPP_G2, NONE),
PAD_NC(GPP_G3, NONE),
- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
+ PAD_CFG_GPO(GPP_G4, 1, DEEP), /* TBT_RTD3_PWR_EN */
+ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* TBT_FORCE_USB_PWR (TBT_RTD3_USB_PWR_EN) */
+ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* -TBT_PERST */
PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
};
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
index 2f0b20d91a..6d8725ad5a 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
@@ -106,6 +106,10 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpHotPlug[8]" = "1"
+
+ chip drivers/intel/dtbt
+ device pci 0.0 on end
+ end
end
# M.2 2280 caddy - x2
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
index a98dd2bc4e..732917ebfa 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C18, NONE),
PAD_NC(GPP_C19, NONE),
PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
+ PAD_CFG_GPO(GPP_C21, 1, DEEP), /* TBT_FORCE_PWR */
PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
@@ -187,9 +187,9 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_G1, NONE),
PAD_NC(GPP_G2, NONE),
PAD_NC(GPP_G3, NONE),
- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
+ PAD_CFG_GPO(GPP_G4, 1, DEEP), /* TBT_RTD3_PWR_EN */
+ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* TBT_FORCE_USB_PWR (TBT_RTD3_USB_PWR_EN) */
+ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* -TBT_PERST */
PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
};
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
index cea5e485d2..9b952215c5 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
@@ -106,6 +106,10 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
+
+ chip drivers/intel/dtbt
+ device pci 0.0 on end
+ end
end
# M.2 2280 SSD - x2
--
2.39.5

3
config/coreboot/t480_fsp_16mb/config/libgfxinit_corebootfb
View File

@@ -115,7 +115,7 @@ CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="lenovo/sklkbl_thinkpad"
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_DIMM_MAX=2
CONFIG_DIMM_SPD_SIZE=256
CONFIG_DIMM_SPD_SIZE=512
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="LENOVO"
@@ -625,6 +625,7 @@ CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_DRIVERS_INTEL_DTBT=y
CONFIG_FSP_USE_REPO=y
# CONFIG_DISPLAY_HOBS is not set
# CONFIG_DISPLAY_UPD_DATA is not set

3
config/coreboot/t480_fsp_16mb/config/libgfxinit_txtmode
View File

@@ -115,7 +115,7 @@ CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="lenovo/sklkbl_thinkpad"
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_DIMM_MAX=2
CONFIG_DIMM_SPD_SIZE=256
CONFIG_DIMM_SPD_SIZE=512
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="LENOVO"
@@ -617,6 +617,7 @@ CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_DRIVERS_INTEL_DTBT=y
CONFIG_FSP_USE_REPO=y
# CONFIG_DISPLAY_HOBS is not set
# CONFIG_DISPLAY_UPD_DATA is not set

3
config/coreboot/t480s_fsp_16mb/config/libgfxinit_corebootfb
View File

@@ -115,7 +115,7 @@ CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="lenovo/sklkbl_thinkpad"
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_DIMM_MAX=2
CONFIG_DIMM_SPD_SIZE=256
CONFIG_DIMM_SPD_SIZE=512
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="LENOVO"
@@ -625,6 +625,7 @@ CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_DRIVERS_INTEL_DTBT=y
CONFIG_FSP_USE_REPO=y
# CONFIG_DISPLAY_HOBS is not set
# CONFIG_DISPLAY_UPD_DATA is not set

3
config/coreboot/t480s_fsp_16mb/config/libgfxinit_txtmode
View File

@@ -115,7 +115,7 @@ CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="lenovo/sklkbl_thinkpad"
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_DIMM_MAX=2
CONFIG_DIMM_SPD_SIZE=256
CONFIG_DIMM_SPD_SIZE=512
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="LENOVO"
@@ -617,6 +617,7 @@ CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_DRIVERS_INTEL_DTBT=y
CONFIG_FSP_USE_REPO=y
# CONFIG_DISPLAY_HOBS is not set
# CONFIG_DISPLAY_UPD_DATA is not set