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cc2f08e7bb
This reverts commit 32dfdfbb01.
The update caused an issue on T480:
Backlight comes on, then off, then on, then off, repeatedly, and
never gets to the payload. Will have to investigate further.
Signed-off-by: Leah Rowe <leah@libreboot.org>
62 lines
1.8 KiB
Diff
62 lines
1.8 KiB
Diff
From 1f13ade55375d32a65eb5e9cf327f7060353a225 Mon Sep 17 00:00:00 2001
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From: Leah Rowe <leah@libreboot.org>
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Date: Mon, 6 Jan 2025 01:36:23 +0000
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Subject: [PATCH 35/41] src/intel/skylake: Disable stack overflow debug options
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The option was appearing in T480/3050micro configs of lbmk,
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after updating on the coreboot/next uprev for 20241206 rev8:
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CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y
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I did some digging. See coreboot commit:
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commit 51cc2bacb6b07279b97e9934d079060475481fb6
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Author: Subrata Banik <subratabanik@google.com>
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Date: Fri Dec 13 13:07:28 2024 +0530
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soc/intel/pantherlake: Disable stack overflow debug options
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Well now:
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I'm disabling this behaviour on Skylake, for the same
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behaviour, because I want as few behaviour changes in general,
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as possible, for the rev8 release.
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According to Subrata's patch, which was for Pantherlake,
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without this change, stack corruption can occur on verstage
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and romstage early on. Please look at that coreboot patch,
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referenced above, for clarity.
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I see no harm in disabling this option for Skylake, since
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the behaviour that it otherwise enables was not present
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before.
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Signed-off-by: Leah Rowe <leah@libreboot.org>
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---
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src/soc/intel/skylake/Kconfig | 9 +++++++++
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1 file changed, 9 insertions(+)
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diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
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index d51ffaef7b..42af82a5d8 100644
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--- a/src/soc/intel/skylake/Kconfig
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+++ b/src/soc/intel/skylake/Kconfig
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@@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
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+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
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+ bool
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+ default n
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+
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+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
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+ bool
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+ default n
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+
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x20400 if FSP_USES_CB_STACK
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--
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2.39.5
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