add heci timeout for ibex peak

patch courtesy of denis :) Signed-off-by: Leah Rowe <leah@libreboot.org>
add lenovo x201 support
2026-03-25 21:39:03 +02:00 · 2023-10-29 11:42:41 +00:00 · 2023-10-29 04:46:25 +00:00 · 2023-10-29 01:29:38 +00:00 · 2023-10-28 21:19:48 +01:00 · 2023-10-25 12:58:52 +01:00
151 changed files with 4187 additions and 247 deletions
--- a/config/coreboot/d510mo/config/libgfxinit_txtmode
+++ b/config/coreboot/d510mo/config/libgfxinit_txtmode
@@ -209,6 +209,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -499,7 +500,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/d510mo_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/d510mo_16mb/config/libgfxinit_txtmode
@@ -209,6 +209,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -499,7 +500,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/default/patches/0024-don-t-use-github-for-the-acpica-download.patch
+++ b/config/coreboot/default/patches/0024-don-t-use-github-for-the-acpica-download.patch
@@ -0,0 +1,39 @@
+From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 22 Oct 2023 15:02:25 +0100
+Subject: [PATCH 1/1] don't use github for the acpica download
+
+i have the tarball from a previous download, and i placed
+it on libreboot rsync, which then got mirrored to princeton.
+
+today, github's ssl cert was b0rking the hell out and i really
+really wanted to finish a build, and didn't want to wait for
+github to fix their httpd.
+
+so i'm now hosting this specific acpica tarball on rsync.
+
+this patch makes that URL be used, instead of the github one.
+
+that's the 2nd time i've had to patch coreboot's acpica download!
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index ebc9fcb49a..a857110b4b 100755
+--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
+@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+ GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+ BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+ CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+
--- a/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch
+++ b/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch
@@ -0,0 +1,341 @@
+From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 29 Oct 2023 01:18:50 +0000
+Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
+ value"
+
+This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
+
+NOTE:
+
+this is done instead of merging:
+https://review.coreboot.org/c/coreboot/+/78623
+
+which is still under review for now
+
+the patch i'm reverting is this one:
+https://review.coreboot.org/c/coreboot/+/78270
+
+this was actually only merged the day before i
+updated coreboot revs in lbmk to the 12 october rev,
+so there's no harm in quickly reverting this for now
+
+however, later on, we will rely on the other patch
+---
+ src/Kconfig                                   | 3 ++-
+ src/cpu/qemu-x86/Kconfig                      | 3 +++
+ src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
+ src/northbridge/amd/pi/Kconfig                | 4 ++++
+ src/soc/amd/picasso/Kconfig                   | 4 ++++
+ src/soc/amd/stoneyridge/Kconfig               | 4 ++++
+ src/soc/cavium/cn81xx/Kconfig                 | 3 +++
+ src/soc/intel/alderlake/Kconfig               | 5 +++++
+ src/soc/intel/apollolake/Kconfig              | 4 ++++
+ src/soc/intel/cannonlake/Kconfig              | 4 ++++
+ src/soc/intel/elkhartlake/Kconfig             | 4 ++++
+ src/soc/intel/jasperlake/Kconfig              | 4 ++++
+ src/soc/intel/meteorlake/Kconfig              | 5 +++++
+ src/soc/intel/skylake/Kconfig                 | 4 ++++
+ src/soc/intel/tigerlake/Kconfig               | 4 ++++
+ src/soc/intel/xeon_sp/Kconfig                 | 4 ++++
+ src/soc/intel/xeon_sp/cpx/Kconfig             | 4 ++++
+ src/soc/intel/xeon_sp/skx/Kconfig             | 4 ++++
+ src/soc/intel/xeon_sp/spr/Kconfig             | 4 ++++
+ src/soc/qualcomm/ipq40xx/Kconfig              | 4 ++++
+ 20 files changed, 77 insertions(+), 1 deletion(-)
+
+diff --git a/src/Kconfig b/src/Kconfig
+index ae8024089e..1549719dd0 100644
+--- a/src/Kconfig
+++ b/src/Kconfig
+@@ -751,7 +751,8 @@ config RTC
+ 
+ config HEAP_SIZE
+ 	hex
+-	default 0x100000
+	default 0x100000 if FLATTENED_DEVICE_TREE
+	default 0x4000
+ 
+ config STACK_SIZE
+ 	hex
+diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
+index 0fa999e1ac..f3e2c4cea9 100644
+--- a/src/cpu/qemu-x86/Kconfig
+++ b/src/cpu/qemu-x86/Kconfig
+@@ -35,4 +35,7 @@ config MAX_CPUS
+ 	default 32 if SMM_TSEG
+ 	default 4
+ 
+config HEAP_SIZE
+	default 0x8000
+
+ endif
+diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
+index 7bc3b0bcbb..7f9300f2a7 100644
+--- a/src/mainboard/sifive/hifive-unleashed/Kconfig
+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
+@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select FLATTENED_DEVICE_TREE
+ 	select SPI_SDCARD
+ 
+config HEAP_SIZE
+	default 0x10000
+
+ config MAINBOARD_DIR
+ 	default "sifive/hifive-unleashed"
+ 
+diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
+index 4ffe82a15f..4518db149b 100644
+--- a/src/northbridge/amd/pi/Kconfig
+++ b/src/northbridge/amd/pi/Kconfig
+@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
+ 	hex
+ 	default 0x200000
+ 
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+ endif # NORTHBRIDGE_AMD_PI
+diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
+index c33f287067..796fe4eb13 100644
+--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
+@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
+ 	bool
+ 	default n
+ 
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+ config SERIRQ_CONTINUOUS_MODE
+ 	bool
+ 	default n
+diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
+index 6ff135e6a8..9af7455bae 100644
+--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
+@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
+ 	bool
+ 	default n
+ 
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+ config EHCI_BAR
+ 	hex
+ 	default 0xfef00000
+diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
+index 77ca97202b..368581f8f1 100644
+--- a/src/soc/cavium/cn81xx/Kconfig
+++ b/src/soc/cavium/cn81xx/Kconfig
+@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
+ 	int
+ 	default 1
+ 
+config HEAP_SIZE
+	default 0x10000
+
+ config STACK_SIZE
+ 	default 0x2000
+ 
+diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
+index 4b960c1d22..82ec8f263e 100644
+--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
+@@ -215,6 +215,11 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000 if BMP_LOGO
+	default 0x10000
+
+ config GFX_GMA_DEFAULT_MMIO
+ 	default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
+ 
+diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
+index 78ec2987ce..bce935d800 100644
+--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
+@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
+ 	help
+ 	  Name of file to store in the IFWI region.
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 6
+diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
+index a42a3c365b..80237f9810 100644
+--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
+@@ -160,6 +160,10 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config NHLT_DMIC_1CH_16B
+ 	bool
+ 	depends on ACPI_NHLT
+diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
+index 3361c0ddb9..7f1c767379 100644
+--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
+@@ -104,6 +104,10 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x0
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 7
+diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
+index 3d84991e09..ff5def3263 100644
+--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
+@@ -106,6 +106,10 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 8
+diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
+index 590e8b80e1..48030a1911 100644
+--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
+@@ -197,6 +197,11 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000 if BMP_LOGO
+	default 0x10000
+
+ # Intel recommends reserving the PCIe TBT root port resources as below:
+ # - 42 buses
+ # - 194 MiB Non-prefetchable memory
+diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
+index e0df501460..d6a11363ee 100644
+--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
+@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
+ 	help
+ 	  If you set this option to n, will not use native SD controller.
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
+index c07a0d8365..0a4b7bfdb8 100644
+--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
+@@ -152,6 +152,10 @@ config IED_REGION_SIZE
+ config INTEL_TME
+ 	default n
+ 
+config HEAP_SIZE
+	hex
+	default 0x10000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 24 if SOC_INTEL_TIGERLAKE_PCH_H
+diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
+index e63bee5451..63ced01067 100644
+--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
+@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
+ config ECAM_MMCONF_BUS_NUMBER
+ 	default 256
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config HPET_MIN_TICKS
+ 	hex
+ 	default 0x80
+diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
+index ac166c3038..f54f7716b6 100644
+--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
+@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
+ 	hex
+ 	default 0x7C00
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config STACK_SIZE
+ 	hex
+ 	default 0x4000
+diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
+index 5d843878e1..c2c3d4e2e8 100644
+--- a/src/soc/intel/xeon_sp/skx/Kconfig
+++ b/src/soc/intel/xeon_sp/skx/Kconfig
+@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
+ 	hex
+ 	default 0x7C00
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
+index 43b87ade14..b1c4c783b7 100644
+--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
+@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
+ 	hex
+ 	default 0x8c00
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config STACK_SIZE
+ 	hex
+ 	default 0x4000
+diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
+index 0ce92731c0..0eabb00752 100644
+--- a/src/soc/qualcomm/ipq40xx/Kconfig
+++ b/src/soc/qualcomm/ipq40xx/Kconfig
+@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
+ 	help
+ 	  Path for utils to combine SBL_ELF and bootblock
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ endif
+-- 
+2.39.2
+
--- a/config/coreboot/default/patches/0026-sb-intel-ibexpeak-setup_heci_uma.c-Add-timeouts-when.patch
+++ b/config/coreboot/default/patches/0026-sb-intel-ibexpeak-setup_heci_uma.c-Add-timeouts-when.patch
@@ -0,0 +1,77 @@
+From 27bf50138af0c5267581f8cc1f80676fb1836572 Mon Sep 17 00:00:00 2001
+From: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
+Date: Mon, 27 Mar 2017 22:05:16 +0200
+Subject: [PATCH 1/1] sb/intel/ibexpeak/setup_heci_uma.c: Add timeouts when
+ waiting for heci
+
+Since until now, the code running on the management engine is:
+- Signed by its manufacturer
+- Proprietary software, without corresponding source code
+It can desirable to run the least ammount possible of such
+code, which is what me_cleaner[1] enables.
+
+It does it by removing partitions of the management engine
+firmwares, however when doing so, the HECI interface might
+not be present anymore.
+
+So it is desirable not to have the RAM initialisation code
+wait forever for the HECI interface to appear.
+
+[1] https://github.com/corna/me_cleaner/
+
+MERGENOTE: Adapted from this patch:
+https://mail.coreboot.org/pipermail/coreboot/2017-March/083798.html
+Author on this version of the patch set to same author as in the
+linked one, with same date set, but the commit message is modified
+to match the new code path. Patch author Denis Carikli, but this
+versions of the patch was rebased from it by Leah Rowe on 29 Oct 2023.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/southbridge/intel/ibexpeak/setup_heci_uma.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
+index 572e5e7a76..3a68344d97 100644
+--- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c
+++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
+@@ -8,28 +8,30 @@
+ #include <southbridge/intel/ibexpeak/me.h>
+ #include <southbridge/intel/ibexpeak/pch.h>
+ #include <types.h>
+#include <delay.h>
+ 
+ #define HECIDEV PCI_DEV(0, 0x16, 0)
+ 
+-/* FIXME: add timeout.  */
+ static void wait_heci_ready(void)
+ {
+-	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8))	// = 0x8000000c
+-		;
+	int i = 1000*1000;
+ 
+	while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8)) /* = 0x8000000c */
+		udelay(1);
+ 	write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
+ }
+ 
+-/* FIXME: add timeout.  */
+ static void wait_heci_cb_avail(int len)
+ {
+	int i = 1000*1000;
+
+ 	union {
+ 		struct mei_csr csr;
+ 		u32 raw;
+ 	} csr;
+ 
+-	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8))
+-		;
+	while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8))
+		udelay(1);
+ 
+ 	do {
+ 		csr.raw = read32(DEFAULT_HECIBAR + 0x4);
+-- 
+2.39.2
+
--- a/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/e6400_4mb/config/libgfxinit_corebootfb
@@ -171,6 +171,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -486,7 +487,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/e6400_4mb/config/libgfxinit_txtmode
+++ b/config/coreboot/e6400_4mb/config/libgfxinit_txtmode
@@ -169,6 +169,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -482,7 +483,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb
@@ -171,6 +171,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -498,7 +499,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/e6430_12mb/config/libgfxinit_txtmode
+++ b/config/coreboot/e6430_12mb/config/libgfxinit_txtmode
@@ -169,6 +169,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -495,7 +496,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/fam15h_rdimm/patches/0010-coreboot-fam15h-use-new-upstream-for-acpica.patch
+++ b/config/coreboot/fam15h_rdimm/patches/0010-coreboot-fam15h-use-new-upstream-for-acpica.patch
@@ -29,7 +29,7 @@ index b75b90a877..e3efa722f1 100755
 BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
 GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
 -IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
-+IASL_ARCHIVE="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
 PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
 EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
 # CLANG toolchain archive locations
--- a/config/coreboot/fam15h_udimm/patches/0010-coreboot-fam15h-use-new-upstream-for-acpica.patch
+++ b/config/coreboot/fam15h_udimm/patches/0010-coreboot-fam15h-use-new-upstream-for-acpica.patch
@@ -29,7 +29,7 @@ index b75b90a877..e3efa722f1 100755
 BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
 GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
 -IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
-+IASL_ARCHIVE="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
 PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
 EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
 # CLANG toolchain archive locations
--- a/config/coreboot/g43t-am3/config/libgfxinit_txtmode
+++ b/config/coreboot/g43t-am3/config/libgfxinit_txtmode
@@ -165,6 +165,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -473,7 +474,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/g43t-am3_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/g43t-am3_16mb/config/libgfxinit_txtmode
@@ -165,6 +165,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -473,7 +474,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode
+++ b/config/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode
@@ -172,6 +172,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -480,7 +481,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/gru_bob/config/libgfxinit_corebootfb
+++ b/config/coreboot/gru_bob/config/libgfxinit_corebootfb
@@ -675,6 +675,7 @@ CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_TTYS0_BAUD=115200
 CONFIG_D3COLD_SUPPORT=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_DRIVER_TPM_SPI_CHIP=0
 # CONFIG_TPM_MEASURED_BOOT is not set
@@ -864,7 +865,6 @@ CONFIG_ACPI_CUSTOM_MADT=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/gru_kevin/config/libgfxinit_corebootfb
+++ b/config/coreboot/gru_kevin/config/libgfxinit_corebootfb
@@ -675,6 +675,7 @@ CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_TTYS0_BAUD=115200
 CONFIG_D3COLD_SUPPORT=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -861,7 +862,6 @@ CONFIG_ACPI_CUSTOM_MADT=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch
+++ b/config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch
@@ -21,7 +21,7 @@ index 3c4b10cc92..0c4262b7b1 100755
 GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
 BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
 -IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
-+IASL_ARCHIVE="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
 # CLANG toolchain archive locations
 LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz"
 CLANG_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/clang-${CLANG_VERSION}.src.tar.xz"
--- a/config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb
@@ -193,6 +193,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_16384=y
@@ -545,7 +546,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode
@@ -191,6 +191,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_16384=y
@@ -542,7 +543,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb
@@ -190,6 +190,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -539,7 +540,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode
@@ -188,6 +188,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -536,7 +537,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb
@@ -189,6 +189,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_16384=y
@@ -537,7 +538,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode
@@ -187,6 +187,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_16384=y
@@ -534,7 +535,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp8200sff_4mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/hp8200sff_4mb/config/libgfxinit_corebootfb
@@ -188,6 +188,7 @@ CONFIG_PCIEXP_ASPM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -524,7 +525,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp8200sff_4mb/config/libgfxinit_txtmode
+++ b/config/coreboot/hp8200sff_4mb/config/libgfxinit_txtmode
@@ -186,6 +186,7 @@ CONFIG_PCIEXP_ASPM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -521,7 +522,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp8200sff_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/hp8200sff_8mb/config/libgfxinit_corebootfb
@@ -188,6 +188,7 @@ CONFIG_PCIEXP_ASPM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -524,7 +525,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp8200sff_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/hp8200sff_8mb/config/libgfxinit_txtmode
@@ -186,6 +186,7 @@ CONFIG_PCIEXP_ASPM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -521,7 +522,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp8300usdt_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/hp8300usdt_16mb/config/libgfxinit_corebootfb
@@ -189,6 +189,7 @@ CONFIG_PCIEXP_ASPM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_16384=y
@@ -526,7 +527,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp8300usdt_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/hp8300usdt_16mb/config/libgfxinit_txtmode
@@ -187,6 +187,7 @@ CONFIG_PCIEXP_ASPM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_16384=y
@@ -523,7 +524,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp8470pintel_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/hp8470pintel_16mb/config/libgfxinit_corebootfb
@@ -192,6 +192,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_16384=y
@@ -543,7 +544,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp8470pintel_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/hp8470pintel_16mb/config/libgfxinit_txtmode
@@ -190,6 +190,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_16384=y
@@ -540,7 +541,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp9470m_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/hp9470m_16mb/config/libgfxinit_corebootfb
@@ -190,6 +190,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_16384=y
@@ -539,7 +540,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/hp9470m_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/hp9470m_16mb/config/libgfxinit_txtmode
@@ -188,6 +188,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_16384=y
@@ -536,7 +537,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/kcma-d8-rdimm_16mb/target.cfg
+++ b/config/coreboot/kcma-d8-rdimm_16mb/target.cfg
@@ -6,5 +6,4 @@ payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
 crossgcc_ada="n"
-microcode_required="n"
 vendorfiles="n"
--- a/config/coreboot/kcma-d8-rdimm_2mb/target.cfg
+++ b/config/coreboot/kcma-d8-rdimm_2mb/target.cfg
@@ -6,5 +6,4 @@ payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
 crossgcc_ada="n"
-microcode_required="n"
 vendorfiles="n"
--- a/config/coreboot/kcma-d8-udimm_16mb/target.cfg
+++ b/config/coreboot/kcma-d8-udimm_16mb/target.cfg
@@ -6,5 +6,4 @@ payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
 crossgcc_ada="n"
-microcode_required="n"
 vendorfiles="n"
--- a/config/coreboot/kcma-d8-udimm_2mb/target.cfg
+++ b/config/coreboot/kcma-d8-udimm_2mb/target.cfg
@@ -6,5 +6,4 @@ payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
 crossgcc_ada="n"
-microcode_required="n"
 vendorfiles="n"
--- a/config/coreboot/kfsn4-dre_1mb/target.cfg
+++ b/config/coreboot/kfsn4-dre_1mb/target.cfg
@@ -4,6 +4,5 @@ arch="x86_64"
 payload_seabios="y"
 payload_memtest="y"
 crossgcc_ada="n"
-microcode_required="n"
 vendorfiles="n"
 grub_timeout=10
--- a/config/coreboot/kfsn4-dre_2mb/target.cfg
+++ b/config/coreboot/kfsn4-dre_2mb/target.cfg
@@ -5,6 +5,5 @@ payload_seabios="y"
 payload_seabios_withgrub="y"
 payload_memtest="y"
 crossgcc_ada="n"
-microcode_required="n"
 vendorfiles="n"
 grub_timeout=10
--- a/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg
+++ b/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg
@@ -5,6 +5,5 @@ payload_seabios="y"
 payload_seabios_withgrub="y"
 payload_memtest="y"
 crossgcc_ada="n"
-microcode_required="n"
 vendorfiles="n"
 grub_timeout=10
--- a/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg
+++ b/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg
@@ -5,6 +5,5 @@ payload_seabios="y"
 payload_seabios_withgrub="y"
 payload_memtest="y"
 crossgcc_ada="n"
-microcode_required="n"
 vendorfiles="n"
 grub_timeout=10
--- a/config/coreboot/kgpe-d16-udimm_16mb/target.cfg
+++ b/config/coreboot/kgpe-d16-udimm_16mb/target.cfg
@@ -5,6 +5,5 @@ payload_seabios="y"
 payload_seabios_withgrub="y"
 payload_memtest="y"
 crossgcc_ada="n"
-microcode_required="n"
 vendorfiles="n"
 grub_timeout=10
--- a/config/coreboot/kgpe-d16-udimm_2mb/target.cfg
+++ b/config/coreboot/kgpe-d16-udimm_2mb/target.cfg
@@ -5,6 +5,5 @@ payload_seabios="y"
 payload_seabios_withgrub="y"
 payload_memtest="y"
 crossgcc_ada="n"
-microcode_required="n"
 vendorfiles="n"
 grub_timeout=10
--- a/config/coreboot/macbook11/config/libgfxinit_corebootfb
+++ b/config/coreboot/macbook11/config/libgfxinit_corebootfb
@@ -162,6 +162,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -458,7 +459,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/macbook11/config/libgfxinit_txtmode
+++ b/config/coreboot/macbook11/config/libgfxinit_txtmode
@@ -162,6 +162,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -456,7 +457,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb
@@ -161,6 +161,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -457,7 +458,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode
@@ -161,6 +161,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -455,7 +456,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/macbook21/config/libgfxinit_corebootfb
+++ b/config/coreboot/macbook21/config/libgfxinit_corebootfb
@@ -162,6 +162,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -458,7 +459,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/macbook21/config/libgfxinit_txtmode
+++ b/config/coreboot/macbook21/config/libgfxinit_txtmode
@@ -162,6 +162,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -456,7 +457,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb
@@ -161,6 +161,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -457,7 +458,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode
@@ -161,6 +161,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -455,7 +456,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/qemu_arm64_12mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/qemu_arm64_12mb/config/libgfxinit_corebootfb
@@ -143,6 +143,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_16384=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -312,7 +313,6 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y
 CONFIG_ACPI_HAVE_PCAT_8259=y
 CONFIG_ACPI_CUSTOM_MADT=y
 CONFIG_BOOT_DEVICE_NOT_SPI_FLASH=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb
@@ -162,6 +162,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x8000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -375,7 +376,6 @@ CONFIG_ACPI_COMMON_MADT_IOAPIC=y
 CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_NOT_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode
+++ b/config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode
@@ -162,6 +162,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x8000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -371,7 +372,6 @@ CONFIG_ACPI_COMMON_MADT_IOAPIC=y
 CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_NOT_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/qemu_x86_12mb/target.cfg
+++ b/config/coreboot/qemu_x86_12mb/target.cfg
@@ -5,6 +5,7 @@ payload_grub="y"
 payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
+payload_uboot="y"
 grub_scan_disk="both"
 vendorfiles="n"
 microcode_required="n"
--- a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/r400_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/r400_16mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/r400_4mb/config/libgfxinit_txtmode
+++ b/config/coreboot/r400_4mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/r400_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/r400_8mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb
@@ -206,6 +206,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -526,7 +527,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/r500_4mb/config/libgfxinit_txtmode
+++ b/config/coreboot/r500_4mb/config/libgfxinit_txtmode
@@ -204,6 +204,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -522,7 +523,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t1650_12mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t1650_12mb/config/libgfxinit_txtmode
@@ -179,6 +179,7 @@ CONFIG_PCIEXP_L1_SUB_STATE=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -515,7 +516,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t400_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t400_16mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t400_4mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t400_4mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t400_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t400_8mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t420_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t420_8mb/config/libgfxinit_corebootfb
@@ -210,6 +210,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -558,7 +559,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb
@@ -210,6 +210,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -557,7 +558,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t420s_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t420s_8mb/config/libgfxinit_txtmode
@@ -208,6 +208,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -554,7 +555,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t430_12mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t430_12mb/config/libgfxinit_corebootfb
@@ -210,6 +210,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -558,7 +559,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t430_12mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t430_12mb/config/libgfxinit_txtmode
@@ -208,6 +208,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -555,7 +556,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -551,7 +552,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -548,7 +549,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t500_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t500_16mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t500_4mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t500_4mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t500_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t500_8mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t520_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t520_8mb/config/libgfxinit_corebootfb
@@ -211,6 +211,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -558,7 +559,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t520_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t520_8mb/config/libgfxinit_txtmode
@@ -209,6 +209,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -555,7 +556,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t530_12mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/t530_12mb/config/libgfxinit_corebootfb
@@ -211,6 +211,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -559,7 +560,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t530_12mb/config/libgfxinit_txtmode
+++ b/config/coreboot/t530_12mb/config/libgfxinit_txtmode
@@ -209,6 +209,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -556,7 +557,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb
+++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb
@@ -199,6 +199,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -505,7 +506,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode
+++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode
@@ -199,6 +199,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -503,7 +504,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb
+++ b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb
@@ -199,6 +199,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -505,7 +506,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode
+++ b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode
@@ -199,6 +199,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -503,7 +504,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/w500_16mb/config/libgfxinit_txtmode
+++ b/config/coreboot/w500_16mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/w500_4mb/config/libgfxinit_txtmode
+++ b/config/coreboot/w500_4mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -529,7 +530,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/w500_8mb/config/libgfxinit_txtmode
+++ b/config/coreboot/w500_8mb/config/libgfxinit_txtmode
@@ -205,6 +205,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -525,7 +526,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/w530_12mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/w530_12mb/config/libgfxinit_corebootfb
@@ -211,6 +211,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -560,7 +561,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/w530_12mb/config/libgfxinit_txtmode
+++ b/config/coreboot/w530_12mb/config/libgfxinit_txtmode
@@ -209,6 +209,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -557,7 +558,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
--- a/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb
+++ b/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb
@@ -207,6 +207,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -550,7 +551,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
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Author	SHA1	Message	Date
Leah Rowe	27efbc6f54	add heci timeout for ibex peak patch courtesy of denis :) Signed-off-by: Leah Rowe <leah@libreboot.org>	2023-10-29 11:42:41 +00:00
Leah Rowe	7e6fd7e5b4	add lenovo x201 support note: me6_update_parser needs to be written, similar to me7_update_parser, to generate the partition tables within intel me6 on lenovo bios updates. the current logic in lbmk goes like this: mkdir -p vendorfiles/cache/ and save your factory dump as: vendorfiles/cache/x201_factory.rom the build system has been modified, in such a way as to support extracting me.bin (which is the full one) and then neutering from this. this is done automatically, if the file is present, but you must first insert that file there, which means you'll need a dump of the original boot flash on your thinkpad x201 Signed-off-by: Leah Rowe <leah@libreboot.org>	2023-10-29 04:46:25 +00:00
Leah Rowe	93458de74a	revert coreboot heap size patch the patch: https://review.coreboot.org/c/coreboot/+/78270 this has been reverted, because it caused s3 resume issues on most intel laptops in libreboot. i was going to merge this instead: https://review.coreboot.org/c/coreboot/+/78623 however, it's under review, and this doesn't change to the old behaviour; it keeps the new universal config, but changes the default we know the old logic works, so keep that for now. in fact, the offending patch was only merged to main in coreboot, one day before i recently updated coreboot revs in coreboot/default - i used a 12 october revision, the patch above is 11 october i then ran "./update trees -u coreboot" which updated the heap sizes back to the old defaults. this should fix s3 suspend/resume where it was broken, in the libreboot `20231021` release - a point release with this and a few other fixes is planned soon. Signed-off-by: Leah Rowe <leah@libreboot.org>	2023-10-29 01:29:38 +00:00
Leah Rowe	83bf237660	coreboot/fam15h: don't set microcode_required the logic for naming coreboot roms is based on whether cpu_microcode_blob.bin would exist in cbfs, and whether deletion was therefore successful. lbmk was naming nomicrocode on fam15h roms on this basis, but the microcode was being inserted as microcode_amd.bin and microcode_amd_fam15h.bin in the recent `20231021` release, the roms were exclusively labeled _nomicrocode in the rom names, but they do in fact contain microcode. i'm fixing it by telling lbmk not to delete microcode. if microcode_required is not set, or it's set to y, then only roms with microcode updates are provided; even if the rom doesn't actually contain it, lbmk will only label it _nomicrocode if that setting is set to n. i'm not bothering to add further complexity to the rom handling logic, because canoeboot now exists anyway (at website https://canoeboot.org/) which is my new version re-implementing the older, inferior version of libreboot so i'm going to: 1) document this as errata in the release 2) cross reference in the freedom status page 3) if someone still isn't happy, i'll say use canoeboot job done. Signed-off-by: Leah Rowe <leah@libreboot.org>	2023-10-28 21:19:48 +01:00
Leah Rowe	5f6ba01d41	include/option.sh: fix i945 bootblock copy it wasn't being copied right the roms under elf/ were being copied, but not the ones under bin/ - i need to audit it further for now, i run modify_coreboot_roms from build/roms instead of update/trees so, the ones under elf/ no longer have bootblocks copied. it's only done in bin/ Signed-off-by: Leah Rowe <leah@libreboot.org>	2023-10-25 12:58:52 +01:00
Leah Rowe	df031d422a	use mirrorservice.org for acpica downloads princeton was down today. kent is probably more reliable. Signed-off-by: Leah Rowe <leah@libreboot.org>	2023-10-25 10:38:46 +01:00
Leah Rowe	85bc915684	build/roms: copy base rom again for u-boot when building only for u-boot, the current script works just fine. however, when building for other payloads in additional to u-boot, the final u-boot stage fails because other payloads are already inserted via cbfs. when we build u-boot, we do that last because we want u-boot setups to only be u-boot, nothing else. this patch enables qemu x86 to build properly with u-boot. Signed-off-by: Leah Rowe <leah@libreboot.org>	2023-10-24 00:14:01 +01:00
Leah Rowe	f1785c3f43	Merge pull request 'u-boot: Add qemu_x86_12mb build again' (#143 ) from alpernebbi/lbmk:uboot-qemu-x86 into master Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/143	2023-10-23 22:42:35 +00:00
Leah Rowe	b353b0c713	Merge pull request 'u-boot: qemu_arm64_12mb: Enable video console' (#142 ) from alpernebbi/lbmk:uboot-qemu-arm64-video into master Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/142	2023-10-23 22:12:52 +00:00
Alper Nebi Yasak	03c830b2e9	u-boot: Add qemu_x86_12mb build again Add a U-Boot build for the qemu_x86_12mb board. The config is a copy of the upstream "coreboot" defconfig, but with OF_EMBED=y. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>	2023-10-23 20:15:19 +03:00
Alper Nebi Yasak	444f2899e6	u-boot: qemu_arm64_12mb: Enable video console Add my upstream U-Boot series enabling video console support by default for QEMU ARM virtual machines. Similarly, enable the related config options for our builds using savedefconfig and olddefconfig. The resulting ROM can be booted with a command line like: qemu-system-aarch64 \ -machine virt,secure=on,virtualization=on \ -cpu cortex-a72 -m 1G \ -serial stdio -device VGA \ -device qemu-xhci \ -device usb-kbd -device usb-mouse \ -bios bin/qemu_arm64_12mb/*.rom Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>	2023-10-23 19:18:14 +03:00
Leah Rowe	280bccebb5	Merge pull request 'arch, fedora38, parabola, void: install python-setuptools' (#141 ) from Riku_V/lbmk:master into master Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/141	2023-10-23 00:33:49 +00:00
Riku Viitanen	3b92ac97b6	arch, fedora38, parabola, void: install python-setuptools gru_bob fails to build without python-setuptools. this isn't a huge issue, because most users probably have it already as many other python programs depend on it too. that's probably why no one noticed until now, when i tried to do this on a fresh artix install uncontaminated by python. i also sorted and deduplicated the packages with 'sort -u'.	2023-10-22 22:24:47 +03:00
Leah Rowe	8dda0d8654	coreboot/default: don't use github on acpica fetch github's httpd b0rked the fuck out and i didn't want to wait for them to fix it (ssl cert error) before i continued a build. i now host the relevant acpica tarball on libreboot rsync, mirrored to princeton. Signed-off-by: Leah Rowe <leah@libreboot.org>	2023-10-22 15:05:49 +01:00
Leah Rowe	e86af9a60a	20231021hotfix: replace x_ with err in some places keymaps weren't being set in keymay.cfg of cbfs, due to use of x_ in the rom script, and x_ doesn't handle quotes or spaces in arguments well. i'm going to remove use of x_ and xx_ (it's in my todo), for next release. for now, hot patch the release. i've gone through and replaced use of x_ with \|\| err, in some places. not just the keymap.cfg command, but others too. in case there are more issues we missed. this commit is being tagged "20231021fix" and i'm using this tag to re-build the `20231021` release. i'll just replace the tarballs in rsync and add errata to the news page announcing the release. all i did was break peoples umlauts, i didn't brick their machines fortunately! very minor bug. anyway, x_/xx_ is a great idea, but sh isn't really designed for that style of programming. i'll go back to using just \|\| err in the next release. Signed-off-by: Leah Rowe <leah@libreboot.org>	2023-10-22 12:34:45 +01:00