mirror of
https://codeberg.org/libreboot/lbmk.git
synced 2026-03-25 21:39:03 +02:00
Compare commits
1 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
|
9acb6a5339 |
2
.gitignore
vendored
2
.gitignore
vendored
@@ -22,7 +22,7 @@
|
||||
/push
|
||||
/version
|
||||
/versiondate
|
||||
/vendorfiles/
|
||||
/vendor/
|
||||
*me.bin
|
||||
*sch5545ec.bin
|
||||
/mrc/
|
||||
|
||||
73
build
73
build
@@ -8,13 +8,10 @@
|
||||
[ "x${DEBUG+set}" = 'xset' ] && set -v
|
||||
set -u -e
|
||||
|
||||
export LC_COLLATE=C
|
||||
export LC_ALL=C
|
||||
|
||||
. "include/err.sh"
|
||||
. "include/option.sh"
|
||||
|
||||
eval "$(setvars "" option aur_notice tmpdir)"
|
||||
eval "$(setvars "" mode option aur_notice tmpdir)"
|
||||
|
||||
tmpdir_was_set="y"
|
||||
set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n"
|
||||
@@ -42,14 +39,11 @@ buildpath="./script/${linkname}"
|
||||
main()
|
||||
{
|
||||
xx_ id -u 1>/dev/null 2>/dev/null
|
||||
[ $# -lt 1 ] && fail "Too few arguments. Try: ${0} help"
|
||||
[ "${1}" = "dependencies" ] && xx_ install_packages $@ && lbmk_exit 0
|
||||
|
||||
initialise_command $@ && shift 1
|
||||
initialise_command $@
|
||||
shift 2
|
||||
|
||||
check_git
|
||||
check_project "fail"
|
||||
git_init
|
||||
|
||||
execute_command $@
|
||||
lbmk_exit 0
|
||||
@@ -57,13 +51,22 @@ main()
|
||||
|
||||
initialise_command()
|
||||
{
|
||||
[ $# -lt 1 ] && fail "Too few arguments. Try: ${0} help"
|
||||
|
||||
mode="${1}"
|
||||
[ "${mode}" != "dependencies" ] || xx_ install_packages $@
|
||||
[ "$(id -u)" != "0" ] || fail "this command as root is not permitted"
|
||||
|
||||
case "${1}" in
|
||||
help) usage ${0} && lbmk_exit 0 ;;
|
||||
list) items "${buildpath}" && lbmk_exit 0 ;;
|
||||
esac
|
||||
option="${1}"
|
||||
[ "${mode}" = "help" ] && usage ${0} && lbmk_exit 0
|
||||
if [ "${mode}" = "list" ]; then
|
||||
listitems "${buildpath}"
|
||||
lbmk_exit 0
|
||||
elif [ $# -lt 2 ]; then
|
||||
usage ${0}
|
||||
lbmk_exit 1
|
||||
fi
|
||||
|
||||
option="${2}"
|
||||
}
|
||||
|
||||
install_packages()
|
||||
@@ -80,29 +83,23 @@ install_packages()
|
||||
. "config/dependencies/${2}"
|
||||
|
||||
xx_ ${pkg_add} ${pkglist}
|
||||
[ -z "${aur_notice}" ] && return 0
|
||||
printf "You must install AUR packages: %s\n" "${aur_notice}" 1>&2
|
||||
}
|
||||
[ "${aur_notice}" = "" ] || \
|
||||
printf "You must install AUR packages: %s\n" "${aur_notice}" 1>&2
|
||||
|
||||
# release archives contain .gitignore, but not .git.
|
||||
# lbmk can be run from lbmk.git, or an archive.
|
||||
git_init()
|
||||
{
|
||||
[ -L ".git" ] && fail "Reference .git is a symlink"
|
||||
[ -e ".git" ] && return 0
|
||||
eval "$(setvars "$(date -Rd @${versiondate})" cdate _nogit)"
|
||||
|
||||
git init || fail "${PWD}: cannot initialise Git repository"
|
||||
git add -A . || fail "${PWD}: cannot add files to Git repository"
|
||||
git commit -m "${projectname} ${version}" --date "${cdate}" || \
|
||||
fail "${PWD}: can't commit ${projectname}/${version}, date ${cdate}"
|
||||
git tag -a "${version}" -m "${projectname} ${version}" || \
|
||||
fail "${PWD}: cannot git-tag ${projectname}/${version}"
|
||||
lbmk_exit 0
|
||||
}
|
||||
|
||||
execute_command()
|
||||
{
|
||||
lbmkcmd="${buildpath}/${option}"
|
||||
if [ "${option}" = "list" ]; then
|
||||
xx_ listitems "${buildpath}/${mode}"
|
||||
lbmk_exit 0
|
||||
fi
|
||||
lbmkcmd="${buildpath}/${mode}/${option}"
|
||||
[ "${lbmkcmd}" = "./script/build/boot/roms" ] && \
|
||||
printf "NOTE: ./build boot roms now: ./build fw coreboot\n" 1>&2
|
||||
[ "${lbmkcmd%/*}" = "./script/update/blobs" ] && \
|
||||
printf "NOTE: ./update blobs is now: ./update vendor\n" 1>&2
|
||||
[ -f "${lbmkcmd}" ] || fail "Invalid command. Run: ${linkpath} help"
|
||||
"${lbmkcmd}" $@ || fail "execute_command: ${lbmkcmd} ${@}"
|
||||
}
|
||||
@@ -111,10 +108,16 @@ usage()
|
||||
{
|
||||
progname=${0}
|
||||
cat <<- EOF
|
||||
USAGE: ${progname} <OPTION>
|
||||
USAGE: ${progname} <MODE> <OPTION>
|
||||
|
||||
possible values for 'OPTION':
|
||||
$(items "${buildpath}")
|
||||
possible values for 'mode':
|
||||
$(listitems "${buildpath}")
|
||||
|
||||
For each of the above modes, you may also do:
|
||||
${progname} <MODE> list
|
||||
|
||||
Example: ./build fw list, which would yield:
|
||||
$(./build fw list)
|
||||
|
||||
Refer to ${projectname} documentation for more info.
|
||||
EOF
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -209,7 +209,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -500,6 +499,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -209,7 +209,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -500,6 +499,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -1,591 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="intel/d945gclf"
|
||||
CONFIG_VGA_BIOS_ID="8086,2772"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Intel"
|
||||
CONFIG_CBFS_SIZE=0x00080000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_IRQ_SLOT_COUNT=18
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
|
||||
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
|
||||
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
|
||||
|
||||
#
|
||||
# Coffeelake RVP
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_D510MO is not set
|
||||
CONFIG_BOARD_INTEL_D945GCLF=y
|
||||
# CONFIG_BOARD_INTEL_DCP847SKE is not set
|
||||
# CONFIG_BOARD_INTEL_DG41WV is not set
|
||||
# CONFIG_BOARD_INTEL_DG43GT is not set
|
||||
# CONFIG_BOARD_INTEL_DQ67SW is not set
|
||||
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
|
||||
# CONFIG_BOARD_INTEL_GLKRVP is not set
|
||||
# CONFIG_BOARD_INTEL_HARCUVAR is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
|
||||
# CONFIG_BOARD_INTEL_LEAFHILL is not set
|
||||
# CONFIG_BOARD_INTEL_MINNOW3 is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
|
||||
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
|
||||
# CONFIG_BOARD_INTEL_STRAGO is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
|
||||
# CONFIG_BOARD_INTEL_WTM2 is not set
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=512
|
||||
CONFIG_ROM_SIZE=0x00080000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_106CX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_441=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_I945=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_LPC47M15X=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_PLUGIN_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
|
||||
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
CONFIG_HAVE_MP_TABLE=y
|
||||
CONFIG_HAVE_PIRQ_TABLE=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_MP_TABLE=y
|
||||
CONFIG_GENERATE_PIRQ_TABLE=y
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
# CONFIG_DEBUG_PIRQ is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,9 +0,0 @@
|
||||
tree="default"
|
||||
romtype="normal"
|
||||
arch="x86_32"
|
||||
payload_grub="n"
|
||||
payload_grub_withseabios="n"
|
||||
payload_seabios="y"
|
||||
payload_memtest="n"
|
||||
vendorfiles="n"
|
||||
microcode_required="n"
|
||||
@@ -1,591 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="intel/d945gclf"
|
||||
CONFIG_VGA_BIOS_ID="8086,2772"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Intel"
|
||||
CONFIG_CBFS_SIZE=0x00800000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_IRQ_SLOT_COUNT=18
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
|
||||
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
|
||||
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
|
||||
|
||||
#
|
||||
# Coffeelake RVP
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_D510MO is not set
|
||||
CONFIG_BOARD_INTEL_D945GCLF=y
|
||||
# CONFIG_BOARD_INTEL_DCP847SKE is not set
|
||||
# CONFIG_BOARD_INTEL_DG41WV is not set
|
||||
# CONFIG_BOARD_INTEL_DG43GT is not set
|
||||
# CONFIG_BOARD_INTEL_DQ67SW is not set
|
||||
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
|
||||
# CONFIG_BOARD_INTEL_GLKRVP is not set
|
||||
# CONFIG_BOARD_INTEL_HARCUVAR is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
|
||||
# CONFIG_BOARD_INTEL_LEAFHILL is not set
|
||||
# CONFIG_BOARD_INTEL_MINNOW3 is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
|
||||
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
|
||||
# CONFIG_BOARD_INTEL_STRAGO is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
|
||||
# CONFIG_BOARD_INTEL_WTM2 is not set
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=8192
|
||||
CONFIG_ROM_SIZE=0x00800000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_106CX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_441=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_I945=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_LPC47M15X=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_PLUGIN_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
|
||||
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
CONFIG_HAVE_MP_TABLE=y
|
||||
CONFIG_HAVE_PIRQ_TABLE=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_MP_TABLE=y
|
||||
CONFIG_GENERATE_PIRQ_TABLE=y
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
# CONFIG_DEBUG_PIRQ is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,9 +0,0 @@
|
||||
tree="default"
|
||||
romtype="normal"
|
||||
arch="x86_32"
|
||||
payload_grub="n"
|
||||
payload_grub_withseabios="n"
|
||||
payload_seabios="y"
|
||||
payload_memtest="n"
|
||||
vendorfiles="n"
|
||||
microcode_required="n"
|
||||
@@ -1,39 +0,0 @@
|
||||
From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 22 Oct 2023 15:02:25 +0100
|
||||
Subject: [PATCH 1/1] don't use github for the acpica download
|
||||
|
||||
i have the tarball from a previous download, and i placed
|
||||
it on libreboot rsync, which then got mirrored to princeton.
|
||||
|
||||
today, github's ssl cert was b0rking the hell out and i really
|
||||
really wanted to finish a build, and didn't want to wait for
|
||||
github to fix their httpd.
|
||||
|
||||
so i'm now hosting this specific acpica tarball on rsync.
|
||||
|
||||
this patch makes that URL be used, instead of the github one.
|
||||
|
||||
that's the 2nd time i've had to patch coreboot's acpica download!
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/crossgcc/buildgcc | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
|
||||
index ebc9fcb49a..a857110b4b 100755
|
||||
--- a/util/crossgcc/buildgcc
|
||||
+++ b/util/crossgcc/buildgcc
|
||||
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
|
||||
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
|
||||
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
|
||||
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
|
||||
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
|
||||
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
|
||||
# CLANG toolchain archive locations
|
||||
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
|
||||
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -1,341 +0,0 @@
|
||||
From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 29 Oct 2023 01:18:50 +0000
|
||||
Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
|
||||
value"
|
||||
|
||||
This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
|
||||
|
||||
NOTE:
|
||||
|
||||
this is done instead of merging:
|
||||
https://review.coreboot.org/c/coreboot/+/78623
|
||||
|
||||
which is still under review for now
|
||||
|
||||
the patch i'm reverting is this one:
|
||||
https://review.coreboot.org/c/coreboot/+/78270
|
||||
|
||||
this was actually only merged the day before i
|
||||
updated coreboot revs in lbmk to the 12 october rev,
|
||||
so there's no harm in quickly reverting this for now
|
||||
|
||||
however, later on, we will rely on the other patch
|
||||
---
|
||||
src/Kconfig | 3 ++-
|
||||
src/cpu/qemu-x86/Kconfig | 3 +++
|
||||
src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
|
||||
src/northbridge/amd/pi/Kconfig | 4 ++++
|
||||
src/soc/amd/picasso/Kconfig | 4 ++++
|
||||
src/soc/amd/stoneyridge/Kconfig | 4 ++++
|
||||
src/soc/cavium/cn81xx/Kconfig | 3 +++
|
||||
src/soc/intel/alderlake/Kconfig | 5 +++++
|
||||
src/soc/intel/apollolake/Kconfig | 4 ++++
|
||||
src/soc/intel/cannonlake/Kconfig | 4 ++++
|
||||
src/soc/intel/elkhartlake/Kconfig | 4 ++++
|
||||
src/soc/intel/jasperlake/Kconfig | 4 ++++
|
||||
src/soc/intel/meteorlake/Kconfig | 5 +++++
|
||||
src/soc/intel/skylake/Kconfig | 4 ++++
|
||||
src/soc/intel/tigerlake/Kconfig | 4 ++++
|
||||
src/soc/intel/xeon_sp/Kconfig | 4 ++++
|
||||
src/soc/intel/xeon_sp/cpx/Kconfig | 4 ++++
|
||||
src/soc/intel/xeon_sp/skx/Kconfig | 4 ++++
|
||||
src/soc/intel/xeon_sp/spr/Kconfig | 4 ++++
|
||||
src/soc/qualcomm/ipq40xx/Kconfig | 4 ++++
|
||||
20 files changed, 77 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/Kconfig b/src/Kconfig
|
||||
index ae8024089e..1549719dd0 100644
|
||||
--- a/src/Kconfig
|
||||
+++ b/src/Kconfig
|
||||
@@ -751,7 +751,8 @@ config RTC
|
||||
|
||||
config HEAP_SIZE
|
||||
hex
|
||||
- default 0x100000
|
||||
+ default 0x100000 if FLATTENED_DEVICE_TREE
|
||||
+ default 0x4000
|
||||
|
||||
config STACK_SIZE
|
||||
hex
|
||||
diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
|
||||
index 0fa999e1ac..f3e2c4cea9 100644
|
||||
--- a/src/cpu/qemu-x86/Kconfig
|
||||
+++ b/src/cpu/qemu-x86/Kconfig
|
||||
@@ -35,4 +35,7 @@ config MAX_CPUS
|
||||
default 32 if SMM_TSEG
|
||||
default 4
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ default 0x8000
|
||||
+
|
||||
endif
|
||||
diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
|
||||
index 7bc3b0bcbb..7f9300f2a7 100644
|
||||
--- a/src/mainboard/sifive/hifive-unleashed/Kconfig
|
||||
+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
|
||||
@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select FLATTENED_DEVICE_TREE
|
||||
select SPI_SDCARD
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ default 0x10000
|
||||
+
|
||||
config MAINBOARD_DIR
|
||||
default "sifive/hifive-unleashed"
|
||||
|
||||
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
|
||||
index 4ffe82a15f..4518db149b 100644
|
||||
--- a/src/northbridge/amd/pi/Kconfig
|
||||
+++ b/src/northbridge/amd/pi/Kconfig
|
||||
@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x200000
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0xc0000
|
||||
+
|
||||
endif # NORTHBRIDGE_AMD_PI
|
||||
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
|
||||
index c33f287067..796fe4eb13 100644
|
||||
--- a/src/soc/amd/picasso/Kconfig
|
||||
+++ b/src/soc/amd/picasso/Kconfig
|
||||
@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
|
||||
bool
|
||||
default n
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0xc0000
|
||||
+
|
||||
config SERIRQ_CONTINUOUS_MODE
|
||||
bool
|
||||
default n
|
||||
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
|
||||
index 6ff135e6a8..9af7455bae 100644
|
||||
--- a/src/soc/amd/stoneyridge/Kconfig
|
||||
+++ b/src/soc/amd/stoneyridge/Kconfig
|
||||
@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
|
||||
bool
|
||||
default n
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0xc0000
|
||||
+
|
||||
config EHCI_BAR
|
||||
hex
|
||||
default 0xfef00000
|
||||
diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
|
||||
index 77ca97202b..368581f8f1 100644
|
||||
--- a/src/soc/cavium/cn81xx/Kconfig
|
||||
+++ b/src/soc/cavium/cn81xx/Kconfig
|
||||
@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
|
||||
int
|
||||
default 1
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ default 0x10000
|
||||
+
|
||||
config STACK_SIZE
|
||||
default 0x2000
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index 4b960c1d22..82ec8f263e 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -215,6 +215,11 @@ config IED_REGION_SIZE
|
||||
hex
|
||||
default 0x400000
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x80000 if BMP_LOGO
|
||||
+ default 0x10000
|
||||
+
|
||||
config GFX_GMA_DEFAULT_MMIO
|
||||
default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
|
||||
|
||||
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
|
||||
index 78ec2987ce..bce935d800 100644
|
||||
--- a/src/soc/intel/apollolake/Kconfig
|
||||
+++ b/src/soc/intel/apollolake/Kconfig
|
||||
@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
|
||||
help
|
||||
Name of file to store in the IFWI region.
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x8000
|
||||
+
|
||||
config MAX_ROOT_PORTS
|
||||
int
|
||||
default 6
|
||||
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
|
||||
index a42a3c365b..80237f9810 100644
|
||||
--- a/src/soc/intel/cannonlake/Kconfig
|
||||
+++ b/src/soc/intel/cannonlake/Kconfig
|
||||
@@ -160,6 +160,10 @@ config IED_REGION_SIZE
|
||||
hex
|
||||
default 0x400000
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x8000
|
||||
+
|
||||
config NHLT_DMIC_1CH_16B
|
||||
bool
|
||||
depends on ACPI_NHLT
|
||||
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
|
||||
index 3361c0ddb9..7f1c767379 100644
|
||||
--- a/src/soc/intel/elkhartlake/Kconfig
|
||||
+++ b/src/soc/intel/elkhartlake/Kconfig
|
||||
@@ -104,6 +104,10 @@ config IED_REGION_SIZE
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x8000
|
||||
+
|
||||
config MAX_ROOT_PORTS
|
||||
int
|
||||
default 7
|
||||
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
|
||||
index 3d84991e09..ff5def3263 100644
|
||||
--- a/src/soc/intel/jasperlake/Kconfig
|
||||
+++ b/src/soc/intel/jasperlake/Kconfig
|
||||
@@ -106,6 +106,10 @@ config IED_REGION_SIZE
|
||||
hex
|
||||
default 0x400000
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x8000
|
||||
+
|
||||
config MAX_ROOT_PORTS
|
||||
int
|
||||
default 8
|
||||
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
|
||||
index 590e8b80e1..48030a1911 100644
|
||||
--- a/src/soc/intel/meteorlake/Kconfig
|
||||
+++ b/src/soc/intel/meteorlake/Kconfig
|
||||
@@ -197,6 +197,11 @@ config IED_REGION_SIZE
|
||||
hex
|
||||
default 0x400000
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x80000 if BMP_LOGO
|
||||
+ default 0x10000
|
||||
+
|
||||
# Intel recommends reserving the PCIe TBT root port resources as below:
|
||||
# - 42 buses
|
||||
# - 194 MiB Non-prefetchable memory
|
||||
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
|
||||
index e0df501460..d6a11363ee 100644
|
||||
--- a/src/soc/intel/skylake/Kconfig
|
||||
+++ b/src/soc/intel/skylake/Kconfig
|
||||
@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
|
||||
help
|
||||
If you set this option to n, will not use native SD controller.
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x80000
|
||||
+
|
||||
config IED_REGION_SIZE
|
||||
hex
|
||||
default 0x400000
|
||||
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
|
||||
index c07a0d8365..0a4b7bfdb8 100644
|
||||
--- a/src/soc/intel/tigerlake/Kconfig
|
||||
+++ b/src/soc/intel/tigerlake/Kconfig
|
||||
@@ -152,6 +152,10 @@ config IED_REGION_SIZE
|
||||
config INTEL_TME
|
||||
default n
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x10000
|
||||
+
|
||||
config MAX_ROOT_PORTS
|
||||
int
|
||||
default 24 if SOC_INTEL_TIGERLAKE_PCH_H
|
||||
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
|
||||
index e63bee5451..63ced01067 100644
|
||||
--- a/src/soc/intel/xeon_sp/Kconfig
|
||||
+++ b/src/soc/intel/xeon_sp/Kconfig
|
||||
@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
|
||||
config ECAM_MMCONF_BUS_NUMBER
|
||||
default 256
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x80000
|
||||
+
|
||||
config HPET_MIN_TICKS
|
||||
hex
|
||||
default 0x80
|
||||
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
|
||||
index ac166c3038..f54f7716b6 100644
|
||||
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
|
||||
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
|
||||
@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
|
||||
hex
|
||||
default 0x7C00
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x80000
|
||||
+
|
||||
config STACK_SIZE
|
||||
hex
|
||||
default 0x4000
|
||||
diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
|
||||
index 5d843878e1..c2c3d4e2e8 100644
|
||||
--- a/src/soc/intel/xeon_sp/skx/Kconfig
|
||||
+++ b/src/soc/intel/xeon_sp/skx/Kconfig
|
||||
@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
|
||||
hex
|
||||
default 0x7C00
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x80000
|
||||
+
|
||||
config IED_REGION_SIZE
|
||||
hex
|
||||
default 0x400000
|
||||
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
|
||||
index 43b87ade14..b1c4c783b7 100644
|
||||
--- a/src/soc/intel/xeon_sp/spr/Kconfig
|
||||
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
|
||||
@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
|
||||
hex
|
||||
default 0x8c00
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x80000
|
||||
+
|
||||
config STACK_SIZE
|
||||
hex
|
||||
default 0x4000
|
||||
diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
|
||||
index 0ce92731c0..0eabb00752 100644
|
||||
--- a/src/soc/qualcomm/ipq40xx/Kconfig
|
||||
+++ b/src/soc/qualcomm/ipq40xx/Kconfig
|
||||
@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
|
||||
help
|
||||
Path for utils to combine SBL_ELF and bootblock
|
||||
|
||||
+config HEAP_SIZE
|
||||
+ hex
|
||||
+ default 0x8000
|
||||
+
|
||||
endif
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -1,77 +0,0 @@
|
||||
From 27bf50138af0c5267581f8cc1f80676fb1836572 Mon Sep 17 00:00:00 2001
|
||||
From: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
|
||||
Date: Mon, 27 Mar 2017 22:05:16 +0200
|
||||
Subject: [PATCH 1/1] sb/intel/ibexpeak/setup_heci_uma.c: Add timeouts when
|
||||
waiting for heci
|
||||
|
||||
Since until now, the code running on the management engine is:
|
||||
- Signed by its manufacturer
|
||||
- Proprietary software, without corresponding source code
|
||||
It can desirable to run the least ammount possible of such
|
||||
code, which is what me_cleaner[1] enables.
|
||||
|
||||
It does it by removing partitions of the management engine
|
||||
firmwares, however when doing so, the HECI interface might
|
||||
not be present anymore.
|
||||
|
||||
So it is desirable not to have the RAM initialisation code
|
||||
wait forever for the HECI interface to appear.
|
||||
|
||||
[1] https://github.com/corna/me_cleaner/
|
||||
|
||||
MERGENOTE: Adapted from this patch:
|
||||
https://mail.coreboot.org/pipermail/coreboot/2017-March/083798.html
|
||||
Author on this version of the patch set to same author as in the
|
||||
linked one, with same date set, but the commit message is modified
|
||||
to match the new code path. Patch author Denis Carikli, but this
|
||||
versions of the patch was rebased from it by Leah Rowe on 29 Oct 2023.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/southbridge/intel/ibexpeak/setup_heci_uma.c | 14 ++++++++------
|
||||
1 file changed, 8 insertions(+), 6 deletions(-)
|
||||
|
||||
diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
|
||||
index 572e5e7a76..3a68344d97 100644
|
||||
--- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c
|
||||
+++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
|
||||
@@ -8,28 +8,30 @@
|
||||
#include <southbridge/intel/ibexpeak/me.h>
|
||||
#include <southbridge/intel/ibexpeak/pch.h>
|
||||
#include <types.h>
|
||||
+#include <delay.h>
|
||||
|
||||
#define HECIDEV PCI_DEV(0, 0x16, 0)
|
||||
|
||||
-/* FIXME: add timeout. */
|
||||
static void wait_heci_ready(void)
|
||||
{
|
||||
- while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c
|
||||
- ;
|
||||
+ int i = 1000*1000;
|
||||
|
||||
+ while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8)) /* = 0x8000000c */
|
||||
+ udelay(1);
|
||||
write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
|
||||
}
|
||||
|
||||
-/* FIXME: add timeout. */
|
||||
static void wait_heci_cb_avail(int len)
|
||||
{
|
||||
+ int i = 1000*1000;
|
||||
+
|
||||
union {
|
||||
struct mei_csr csr;
|
||||
u32 raw;
|
||||
} csr;
|
||||
|
||||
- while (!(read32(DEFAULT_HECIBAR + 0xc) & 8))
|
||||
- ;
|
||||
+ while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8))
|
||||
+ udelay(1);
|
||||
|
||||
do {
|
||||
csr.raw = read32(DEFAULT_HECIBAR + 0x4);
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -1,216 +0,0 @@
|
||||
From e047dc3c95063f27517cd6754e9cbe496ac9313d Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Mon, 10 May 2021 22:40:59 +0200
|
||||
Subject: [PATCH] [NOT FOR MERGE] nb/intel/gm45: Make DDR2 raminit work
|
||||
|
||||
List of changes:
|
||||
- Update some timing and ODT values
|
||||
- Patch RCOMP calibration to better match what MRC binaries do
|
||||
- Replay a hardcoded list of RCOMP codes after RcvEn
|
||||
|
||||
This makes raminit work at DDR2-800 speeds and fixes S3 resume as well.
|
||||
Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs.
|
||||
|
||||
Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
|
||||
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
|
||||
index f28c6d1..bdf0432 100644
|
||||
--- a/src/northbridge/intel/gm45/gm45.h
|
||||
+++ b/src/northbridge/intel/gm45/gm45.h
|
||||
@@ -419,7 +419,7 @@
|
||||
int raminit_read_vco_index(void);
|
||||
u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
|
||||
|
||||
-void raminit_rcomp_calibration(stepping_t stepping);
|
||||
+void raminit_rcomp_calibration(int ddr_type, stepping_t stepping);
|
||||
void raminit_reset_readwrite_pointers(void);
|
||||
void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
|
||||
void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
|
||||
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
|
||||
index ecada7b..2b8c44e 100644
|
||||
--- a/src/northbridge/intel/gm45/raminit.c
|
||||
+++ b/src/northbridge/intel/gm45/raminit.c
|
||||
@@ -1049,7 +1049,7 @@
|
||||
}
|
||||
|
||||
/* Perform RCOMP calibration for DDR3. */
|
||||
- raminit_rcomp_calibration(stepping);
|
||||
+ raminit_rcomp_calibration(spd_type, stepping);
|
||||
|
||||
/* Run initial RCOMP. */
|
||||
mchbar_setbits32(0x418, 1 << 17);
|
||||
@@ -1119,7 +1119,7 @@
|
||||
reg = (reg & ~(0xf << 10)) | (2 << 10);
|
||||
else
|
||||
reg = (reg & ~(0xf << 10)) | (3 << 10);
|
||||
- reg = (reg & ~(0x7 << 5)) | (3 << 5);
|
||||
+ reg = (reg & ~(0x7 << 5)) | (2 << 5);
|
||||
} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
|
||||
reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
|
||||
reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
|
||||
@@ -1288,11 +1288,11 @@
|
||||
reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32));
|
||||
reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32));
|
||||
if (timings->mem_clock == MEM_CLOCK_667MT) {
|
||||
- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32));
|
||||
- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32));
|
||||
+ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32));
|
||||
+ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32));
|
||||
} else {
|
||||
- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32));
|
||||
- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32));
|
||||
+ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32));
|
||||
+ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32));
|
||||
}
|
||||
mchbar_write32(CxODT_HIGH(ch), reg);
|
||||
|
||||
@@ -2217,6 +2217,84 @@
|
||||
raminit_write_training(timings->mem_clock, dimms, s3resume);
|
||||
}
|
||||
|
||||
+ /*
|
||||
+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
|
||||
+ * after receiver enable calibration, otherwise raminit sometimes
|
||||
+ * completes with non-working memory.
|
||||
+ */
|
||||
+ mchbar_write32(0x0530, 0x06060005);
|
||||
+ mchbar_write32(0x0680, 0x06060606);
|
||||
+ mchbar_write32(0x0684, 0x08070606);
|
||||
+ mchbar_write32(0x0688, 0x0e0e0c0a);
|
||||
+ mchbar_write32(0x068c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0698, 0x06060606);
|
||||
+ mchbar_write32(0x069c, 0x08070606);
|
||||
+ mchbar_write32(0x06a0, 0x0c0c0b0a);
|
||||
+ mchbar_write32(0x06a4, 0x0c0c0c0c);
|
||||
+
|
||||
+ mchbar_write32(0x06c0, 0x02020202);
|
||||
+ mchbar_write32(0x06c4, 0x03020202);
|
||||
+ mchbar_write32(0x06c8, 0x04040403);
|
||||
+ mchbar_write32(0x06cc, 0x04040404);
|
||||
+ mchbar_write32(0x06d8, 0x02020202);
|
||||
+ mchbar_write32(0x06dc, 0x03020202);
|
||||
+ mchbar_write32(0x06e0, 0x04040403);
|
||||
+ mchbar_write32(0x06e4, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0700, 0x02020202);
|
||||
+ mchbar_write32(0x0704, 0x03020202);
|
||||
+ mchbar_write32(0x0708, 0x04040403);
|
||||
+ mchbar_write32(0x070c, 0x04040404);
|
||||
+ mchbar_write32(0x0718, 0x02020202);
|
||||
+ mchbar_write32(0x071c, 0x03020202);
|
||||
+ mchbar_write32(0x0720, 0x04040403);
|
||||
+ mchbar_write32(0x0724, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0740, 0x02020202);
|
||||
+ mchbar_write32(0x0744, 0x03020202);
|
||||
+ mchbar_write32(0x0748, 0x04040403);
|
||||
+ mchbar_write32(0x074c, 0x04040404);
|
||||
+ mchbar_write32(0x0758, 0x02020202);
|
||||
+ mchbar_write32(0x075c, 0x03020202);
|
||||
+ mchbar_write32(0x0760, 0x04040403);
|
||||
+ mchbar_write32(0x0764, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0780, 0x06060606);
|
||||
+ mchbar_write32(0x0784, 0x09070606);
|
||||
+ mchbar_write32(0x0788, 0x0e0e0c0b);
|
||||
+ mchbar_write32(0x078c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0798, 0x06060606);
|
||||
+ mchbar_write32(0x079c, 0x09070606);
|
||||
+ mchbar_write32(0x07a0, 0x0d0d0c0b);
|
||||
+ mchbar_write32(0x07a4, 0x0d0d0d0d);
|
||||
+
|
||||
+ mchbar_write32(0x07c0, 0x06060606);
|
||||
+ mchbar_write32(0x07c4, 0x09070606);
|
||||
+ mchbar_write32(0x07c8, 0x0e0e0c0b);
|
||||
+ mchbar_write32(0x07cc, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x07d8, 0x06060606);
|
||||
+ mchbar_write32(0x07dc, 0x09070606);
|
||||
+ mchbar_write32(0x07e0, 0x0d0d0c0b);
|
||||
+ mchbar_write32(0x07e4, 0x0d0d0d0d);
|
||||
+
|
||||
+ mchbar_write32(0x0840, 0x06060606);
|
||||
+ mchbar_write32(0x0844, 0x08070606);
|
||||
+ mchbar_write32(0x0848, 0x0e0e0c0a);
|
||||
+ mchbar_write32(0x084c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0858, 0x06060606);
|
||||
+ mchbar_write32(0x085c, 0x08070606);
|
||||
+ mchbar_write32(0x0860, 0x0c0c0b0a);
|
||||
+ mchbar_write32(0x0864, 0x0c0c0c0c);
|
||||
+
|
||||
+ mchbar_write32(0x0880, 0x02020202);
|
||||
+ mchbar_write32(0x0884, 0x03020202);
|
||||
+ mchbar_write32(0x0888, 0x04040403);
|
||||
+ mchbar_write32(0x088c, 0x04040404);
|
||||
+ mchbar_write32(0x0898, 0x02020202);
|
||||
+ mchbar_write32(0x089c, 0x03020202);
|
||||
+ mchbar_write32(0x08a0, 0x04040403);
|
||||
+ mchbar_write32(0x08a4, 0x04040404);
|
||||
+
|
||||
igd_compute_ggc(sysinfo);
|
||||
|
||||
/* Program final memory map (with real values). */
|
||||
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
index aef863f..b74765f 100644
|
||||
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
@@ -161,11 +161,13 @@
|
||||
mchbar += 4;
|
||||
}
|
||||
}
|
||||
-void raminit_rcomp_calibration(const stepping_t stepping) {
|
||||
+void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
|
||||
const int a1step = stepping >= STEPPING_CONVERSION_A1;
|
||||
|
||||
int i;
|
||||
|
||||
+ char magic_comp[2] = {0};
|
||||
+
|
||||
enum {
|
||||
PULL_UP = 0,
|
||||
PULL_DOWN = 1,
|
||||
@@ -196,6 +198,10 @@
|
||||
reg = mchbar_read32(0x518);
|
||||
lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
|
||||
lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
|
||||
+ if (i == 1) {
|
||||
+ magic_comp[0] = (reg >> 8) & 0x3f;
|
||||
+ magic_comp[1] = (reg >> 0) & 0x3f;
|
||||
+ }
|
||||
}
|
||||
/* Cleanup? */
|
||||
mchbar_setbits32(0x400, 1 << 3);
|
||||
@@ -216,13 +222,19 @@
|
||||
for (channel = 0; channel < 2; ++channel) {
|
||||
for (group = 0; group < 6; ++group) {
|
||||
for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) {
|
||||
- lookup_and_write(
|
||||
- a1step,
|
||||
- lut_idx[channel][group][pu_pd] - 7,
|
||||
- ddr3_lookup_schedule[group][pu_pd],
|
||||
- mchbar);
|
||||
+ if (ddr_type == DDR3) {
|
||||
+ lookup_and_write(
|
||||
+ a1step,
|
||||
+ lut_idx[channel][group][pu_pd] - 7,
|
||||
+ ddr3_lookup_schedule[group][pu_pd],
|
||||
+ mchbar);
|
||||
+ }
|
||||
mchbar += 0x0018;
|
||||
}
|
||||
+ if (ddr_type == DDR2) {
|
||||
+ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24);
|
||||
+ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0);
|
||||
+ }
|
||||
mchbar += 0x0010;
|
||||
/* Channel B knows only the first two groups. */
|
||||
if ((1 == channel) && (1 == group))
|
||||
@@ -230,4 +242,7 @@
|
||||
}
|
||||
mchbar += 0x0040;
|
||||
}
|
||||
+
|
||||
+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
|
||||
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
|
||||
}
|
||||
@@ -1,142 +0,0 @@
|
||||
From 0721e7e984bc83861bce3d47632b717848673749 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Tue, 31 Oct 2023 18:24:39 +0000
|
||||
Subject: [PATCH 1/1] crank up vram allocation on more intel boards
|
||||
|
||||
these were added to libreboot, and it's a policy of
|
||||
libreboot to max out the vram settings. this was
|
||||
overlooked, in prior revisions and releases.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/dell/e6400/cmos.default | 2 +-
|
||||
src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
|
||||
src/mainboard/hp/compaq_8200_elite_sff/cmos.default | 2 +-
|
||||
src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
|
||||
src/mainboard/hp/snb_ivb_laptops/cmos.default | 1 +
|
||||
src/mainboard/lenovo/t420/cmos.default | 1 +
|
||||
src/mainboard/lenovo/t420s/cmos.default | 1 +
|
||||
src/mainboard/lenovo/t430/cmos.default | 1 +
|
||||
src/mainboard/lenovo/t520/cmos.default | 1 +
|
||||
src/mainboard/lenovo/t530/cmos.default | 1 +
|
||||
src/mainboard/lenovo/x201/cmos.default | 1 +
|
||||
src/mainboard/lenovo/x220/cmos.default | 1 +
|
||||
12 files changed, 12 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
|
||||
index eeb6f47364..25dfa38cb5 100644
|
||||
--- a/src/mainboard/dell/e6400/cmos.default
|
||||
+++ b/src/mainboard/dell/e6400/cmos.default
|
||||
@@ -2,4 +2,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
power_on_after_fail=Disable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=32M
|
||||
+gfx_uma_size=256M
|
||||
diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
|
||||
index ccc7e64625..7c97b84baf 100644
|
||||
--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
|
||||
+++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
|
||||
@@ -3,5 +3,5 @@ debug_level=Debug
|
||||
power_on_after_fail=Disable
|
||||
nmi=Enable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=128M
|
||||
+gfx_uma_size=224M
|
||||
fan_full_speed=Disable
|
||||
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
|
||||
index 6d27a79c66..4517ffc7c2 100644
|
||||
--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
|
||||
+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
|
||||
@@ -3,5 +3,5 @@ debug_level=Debug
|
||||
power_on_after_fail=Enable
|
||||
nmi=Enable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=32M
|
||||
+gfx_uma_size=224M
|
||||
psu_fan_lvl=3
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
|
||||
index 6f3cec735e..9fc4db2990 100644
|
||||
--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
|
||||
@@ -3,4 +3,4 @@ debug_level=Debug
|
||||
power_on_after_fail=Enable
|
||||
nmi=Enable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=32M
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
|
||||
index ad822d5043..89418a4cfc 100644
|
||||
--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
|
||||
+++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
|
||||
@@ -3,3 +3,4 @@ debug_level=Debug
|
||||
power_on_after_fail=Disable
|
||||
nmi=Enable
|
||||
sata_mode=AHCI
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
|
||||
index c011867916..83f590d39d 100644
|
||||
--- a/src/mainboard/lenovo/t420/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t420/cmos.default
|
||||
@@ -15,3 +15,4 @@ trackpoint=Enable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
|
||||
index c011867916..83f590d39d 100644
|
||||
--- a/src/mainboard/lenovo/t420s/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t420s/cmos.default
|
||||
@@ -15,3 +15,4 @@ trackpoint=Enable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
|
||||
index 55e1e6c04e..a72108f47e 100644
|
||||
--- a/src/mainboard/lenovo/t430/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t430/cmos.default
|
||||
@@ -16,3 +16,4 @@ backlight=Both
|
||||
usb_always_on=Disable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
|
||||
index b66f7034dc..a73ea6e9ee 100644
|
||||
--- a/src/mainboard/lenovo/t520/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t520/cmos.default
|
||||
@@ -16,3 +16,4 @@ backlight=Both
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
|
||||
index b66f7034dc..a73ea6e9ee 100644
|
||||
--- a/src/mainboard/lenovo/t530/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t530/cmos.default
|
||||
@@ -16,3 +16,4 @@ backlight=Both
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
|
||||
index 2cf484fd5a..46294d91ca 100644
|
||||
--- a/src/mainboard/lenovo/x201/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x201/cmos.default
|
||||
@@ -15,3 +15,4 @@ power_management_beeps=Enable
|
||||
low_battery_beep=Enable
|
||||
sata_mode=AHCI
|
||||
usb_always_on=Disable
|
||||
+gfx_uma_size=128M
|
||||
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
|
||||
index 52f303dfdb..92a2026542 100644
|
||||
--- a/src/mainboard/lenovo/x220/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x220/cmos.default
|
||||
@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable
|
||||
sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -171,7 +171,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -487,6 +486,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -169,7 +169,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -483,6 +482,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -5,7 +5,5 @@ payload_grub="n"
|
||||
payload_grub_withseabios="n"
|
||||
payload_seabios="y"
|
||||
payload_memtest="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_seabios_grubonly="y"
|
||||
grub_scan_disk="ahci"
|
||||
microcode_required="n"
|
||||
|
||||
@@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -149,7 +149,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/e6430/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/e6430/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/e6430/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/e6430/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -171,7 +171,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -499,6 +498,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -147,7 +147,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/e6430/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/e6430/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/e6430/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/e6430/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -169,7 +169,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -496,6 +495,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -2,10 +2,7 @@ tree="default"
|
||||
romtype="normal"
|
||||
arch="x86_64"
|
||||
payload_grub="n"
|
||||
payload_grub_withseabios="n"
|
||||
payload_seabios_withgrub="n"
|
||||
payload_seabios="y"
|
||||
payload_memtest="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_seabios_grubonly="y"
|
||||
grub_scan_disk="ahci"
|
||||
microcode_required="n"
|
||||
|
||||
@@ -29,7 +29,7 @@ index b75b90a877..e3efa722f1 100755
|
||||
BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
|
||||
GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
|
||||
-IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
|
||||
+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
|
||||
+IASL_ARCHIVE="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
|
||||
PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
|
||||
EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
|
||||
# CLANG toolchain archive locations
|
||||
|
||||
@@ -29,7 +29,7 @@ index b75b90a877..e3efa722f1 100755
|
||||
BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
|
||||
GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
|
||||
-IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
|
||||
+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
|
||||
+IASL_ARCHIVE="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
|
||||
PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
|
||||
EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
|
||||
# CLANG toolchain archive locations
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -165,7 +165,6 @@ CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -474,6 +473,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -165,7 +165,6 @@ CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -474,6 +473,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -172,7 +172,6 @@ CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -481,6 +480,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -675,7 +675,6 @@ CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_DRIVER_TPM_SPI_CHIP=0
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
@@ -865,6 +864,7 @@ CONFIG_ACPI_CUSTOM_MADT=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -675,7 +675,6 @@ CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -862,6 +861,7 @@ CONFIG_ACPI_CUSTOM_MADT=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -21,7 +21,7 @@ index 3c4b10cc92..0c4262b7b1 100755
|
||||
GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
|
||||
BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
|
||||
-IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
|
||||
+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
|
||||
+IASL_ARCHIVE="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
|
||||
# CLANG toolchain archive locations
|
||||
LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz"
|
||||
CLANG_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/clang-${CLANG_VERSION}.src.tar.xz"
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -150,7 +150,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp_ivybridge/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -193,7 +193,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
@@ -546,6 +545,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -148,7 +148,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp_ivybridge/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -191,7 +191,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
@@ -543,6 +542,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -148,7 +148,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_sandybridge/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_sandybridge/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp_sandybridge/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_sandybridge/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -190,7 +190,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -540,6 +539,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -146,7 +146,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_sandybridge/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_sandybridge/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp_sandybridge/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_sandybridge/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -188,7 +188,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -537,6 +536,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -147,7 +147,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp_ivybridge/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -189,7 +189,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
@@ -538,6 +537,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -145,7 +145,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp_ivybridge/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -187,7 +187,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
@@ -535,6 +534,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -148,7 +148,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp8200sff/ifd_4mb"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp8200sff/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp8200sff/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp8200sff/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -188,7 +188,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -525,6 +524,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -146,7 +146,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp8200sff/ifd_4mb"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp8200sff/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp8200sff/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp8200sff/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -186,7 +186,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -522,6 +521,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -148,7 +148,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp8200sff/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp8200sff/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp8200sff/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp8200sff/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -188,7 +188,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -525,6 +524,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -146,7 +146,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp8200sff/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp8200sff/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp8200sff/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp8200sff/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -186,7 +186,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -522,6 +521,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -148,7 +148,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp8300usdt/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp8300usdt/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp8300usdt/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp8300usdt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -189,7 +189,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
@@ -527,6 +526,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -146,7 +146,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp8300usdt/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp8300usdt/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp8300usdt/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp8300usdt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -187,7 +187,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
@@ -524,6 +523,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -149,7 +149,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp_ivybridge/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -192,7 +192,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
@@ -544,6 +543,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -147,7 +147,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp_ivybridge/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -190,7 +190,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
@@ -541,6 +540,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -148,7 +148,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp_ivybridge/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -190,7 +190,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
@@ -540,6 +539,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -146,7 +146,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/hp_ivybridge/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -188,7 +188,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
@@ -537,6 +536,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -6,4 +6,5 @@ payload_grub_withseabios="y"
|
||||
payload_seabios="y"
|
||||
payload_memtest="y"
|
||||
crossgcc_ada="n"
|
||||
microcode_required="n"
|
||||
vendorfiles="n"
|
||||
|
||||
@@ -6,4 +6,5 @@ payload_grub_withseabios="y"
|
||||
payload_seabios="y"
|
||||
payload_memtest="y"
|
||||
crossgcc_ada="n"
|
||||
microcode_required="n"
|
||||
vendorfiles="n"
|
||||
|
||||
@@ -6,4 +6,5 @@ payload_grub_withseabios="y"
|
||||
payload_seabios="y"
|
||||
payload_memtest="y"
|
||||
crossgcc_ada="n"
|
||||
microcode_required="n"
|
||||
vendorfiles="n"
|
||||
|
||||
@@ -6,4 +6,5 @@ payload_grub_withseabios="y"
|
||||
payload_seabios="y"
|
||||
payload_memtest="y"
|
||||
crossgcc_ada="n"
|
||||
microcode_required="n"
|
||||
vendorfiles="n"
|
||||
|
||||
@@ -4,5 +4,6 @@ arch="x86_64"
|
||||
payload_seabios="y"
|
||||
payload_memtest="y"
|
||||
crossgcc_ada="n"
|
||||
microcode_required="n"
|
||||
vendorfiles="n"
|
||||
grub_timeout=10
|
||||
|
||||
@@ -5,5 +5,6 @@ payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_memtest="y"
|
||||
crossgcc_ada="n"
|
||||
microcode_required="n"
|
||||
vendorfiles="n"
|
||||
grub_timeout=10
|
||||
|
||||
@@ -5,5 +5,6 @@ payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_memtest="y"
|
||||
crossgcc_ada="n"
|
||||
microcode_required="n"
|
||||
vendorfiles="n"
|
||||
grub_timeout=10
|
||||
|
||||
@@ -5,5 +5,6 @@ payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_memtest="y"
|
||||
crossgcc_ada="n"
|
||||
microcode_required="n"
|
||||
vendorfiles="n"
|
||||
grub_timeout=10
|
||||
|
||||
@@ -5,5 +5,6 @@ payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_memtest="y"
|
||||
crossgcc_ada="n"
|
||||
microcode_required="n"
|
||||
vendorfiles="n"
|
||||
grub_timeout=10
|
||||
|
||||
@@ -5,5 +5,6 @@ payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_memtest="y"
|
||||
crossgcc_ada="n"
|
||||
microcode_required="n"
|
||||
vendorfiles="n"
|
||||
grub_timeout=10
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -162,7 +162,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -459,6 +458,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -162,7 +162,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -457,6 +456,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -161,7 +161,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -458,6 +457,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -161,7 +161,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -456,6 +455,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -162,7 +162,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -459,6 +458,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -162,7 +162,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -457,6 +456,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -161,7 +161,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -458,6 +457,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -161,7 +161,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -456,6 +455,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -143,7 +143,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -313,6 +312,7 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_CUSTOM_MADT=y
|
||||
CONFIG_BOOT_DEVICE_NOT_SPI_FLASH=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -162,7 +162,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x8000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -376,6 +375,7 @@ CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_NOT_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -162,7 +162,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x8000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -372,6 +371,7 @@ CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_NOT_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -5,7 +5,6 @@ payload_grub="y"
|
||||
payload_grub_withseabios="y"
|
||||
payload_seabios="y"
|
||||
payload_memtest="y"
|
||||
payload_uboot="y"
|
||||
grub_scan_disk="both"
|
||||
vendorfiles="n"
|
||||
microcode_required="n"
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -530,6 +529,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -526,6 +525,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -530,6 +529,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -526,6 +525,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -530,6 +529,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -526,6 +525,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -206,7 +206,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -527,6 +526,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -204,7 +204,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -523,6 +522,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -140,7 +140,7 @@ CONFIG_TPM_PIRQ=0x0
|
||||
CONFIG_BOARD_DELL_PRECISION_T1650=y
|
||||
CONFIG_BOARD_DELL_SNB_IVB_WORKSTATIONS=y
|
||||
CONFIG_INCLUDE_SMSC_SCH5545_EC_FW=y
|
||||
CONFIG_SMSC_SCH5545_EC_FW_FILE="../../../vendorfiles/t1650/sch5545ec.bin"
|
||||
CONFIG_SMSC_SCH5545_EC_FW_FILE="../../../vendor/t1650/sch5545ec.bin"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
@@ -155,7 +155,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/t1650/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t1650/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/t1650/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/t1650/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -179,7 +179,6 @@ CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
@@ -516,6 +515,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -3,6 +3,5 @@ romtype="normal"
|
||||
arch="x86_64"
|
||||
payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_seabios_grubonly="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="ahci"
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -530,6 +529,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -526,6 +525,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -530,6 +529,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -526,6 +525,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -530,6 +529,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -526,6 +525,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -150,7 +150,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/xx20/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/xx20/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/xx20/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/xx20/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -210,7 +210,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -559,6 +558,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -150,7 +150,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/xx20/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/xx20/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/xx20/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/xx20/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -210,7 +210,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -558,6 +557,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -148,7 +148,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/xx20/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/xx20/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/xx20/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/xx20/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -208,7 +208,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -555,6 +554,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -149,7 +149,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/xx30/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/xx30/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/xx30/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/xx30/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -210,7 +210,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
@@ -559,6 +558,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -147,7 +147,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/xx30/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/xx30/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/xx30/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/xx30/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -208,7 +208,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
@@ -556,6 +555,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -31,8 +31,8 @@ CONFIG_USE_BLOBS=y
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -143,7 +143,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
|
||||
@@ -33,8 +33,8 @@ CONFIG_USE_BLOBS=y
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -146,7 +146,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
@@ -207,7 +207,6 @@ CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
@@ -552,6 +551,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -33,8 +33,8 @@ CONFIG_USE_BLOBS=y
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -144,7 +144,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
@@ -205,7 +205,6 @@ CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
@@ -549,6 +548,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -530,6 +529,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -526,6 +525,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -530,6 +529,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -526,6 +525,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -530,6 +529,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -526,6 +525,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -150,7 +150,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/xx20/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/xx20/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/xx20/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/xx20/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -211,7 +211,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -559,6 +558,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -148,7 +148,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/xx20/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/xx20/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/xx20/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/xx20/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -209,7 +209,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
@@ -556,6 +555,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -149,7 +149,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/xx30/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/xx30/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/xx30/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/xx30/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -211,7 +211,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
@@ -560,6 +559,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -147,7 +147,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/xx30/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/xx30/me.bin"
|
||||
CONFIG_ME_BIN_PATH="../../../vendor/xx30/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/xx30/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
@@ -209,7 +209,6 @@ CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
@@ -557,6 +556,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
@@ -32,8 +32,8 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
@@ -199,7 +199,6 @@ CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x4000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -506,6 +505,7 @@ CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user