9020 sff/mt: add tpm enable patch from mate kukri

Signed-off-by: Leah Rowe <leah@libreboot.org>

build

@@ -13,22 +13,10 @@ export LC_ALL=C
 . "include/err.sh"
 . "include/option.sh"
 
-eval "$(setvars "" option aur_notice tmpdir)"
-err="fail"
+export LBMK_RELEASE="$lbmk_release"
 
-tmpdir_was_set="y"
-set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n"
-if [ "${tmpdir_was_set}" = "y" ]; then
-	[ "${TMPDIR%_*}" = "/tmp/lbmk" ] || tmpdir_was_set="n"
-fi
-if [ "${tmpdir_was_set}" = "n" ]; then
-	export TMPDIR="/tmp"
-	tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)"
-	export TMPDIR="${tmpdir}"
-else
-	export TMPDIR="${TMPDIR}"
-	tmpdir="${TMPDIR}"
-fi
+eval "$(setvars "" option aur_notice)"
+err="fail"
 
 linkpath="${0}"
 linkname="${linkpath##*/}"

config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch

@@ -1,13 +1,13 @@
-From f6340f3fe21e948ba94d0429467882c2fb90b77e Mon Sep 17 00:00:00 2001
+From c58e0fea2a4e591e5ecd8a1f376c3b3af0fbb306 Mon Sep 17 00:00:00 2001
 From: Mate Kukri <kukri.mate@gmail.com>
-Date: Sat, 6 Apr 2024 23:25:15 +0100
+Date: Thu, 18 Apr 2024 20:28:45 +0100
 Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization
 
 There are 4 different chassis types specified by vendor firmware, each
 with a slightly different HWM configuration.
 
 The chassis type to use is determined at runtime by reading a set of
-4 PCH GPIOs: 70, 38, 17, and 0.
+4 PCH GPIOs: 70, 38, 17, and 1.
 
 Additionally vendor firmware also provides an option to run the fans at
 full speed. This is substituted with a coreboot nvram option in this
@@ -26,10 +26,10 @@ Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
  src/mainboard/dell/optiplex_9020/bootblock.c  |  25 +-
  src/mainboard/dell/optiplex_9020/cmos.default |   1 +
  src/mainboard/dell/optiplex_9020/cmos.layout  |   5 +-
- src/mainboard/dell/optiplex_9020/mainboard.c  | 382 ++++++++++++++++++
+ src/mainboard/dell/optiplex_9020/mainboard.c  | 387 ++++++++++++++++++
  src/mainboard/dell/optiplex_9020/sch5555_ec.c |  54 +++
- src/mainboard/dell/optiplex_9020/sch5555_ec.h |   7 +
- 7 files changed, 455 insertions(+), 22 deletions(-)
+ src/mainboard/dell/optiplex_9020/sch5555_ec.h |  10 +
+ 7 files changed, 463 insertions(+), 22 deletions(-)
  create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c
  create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h
 
@@ -119,7 +119,7 @@ index 72ff9c4bee..4a1496a878 100644
  # coreboot config options: check sums
  984	16	h	0	check_sum
 diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
-index c834fea5d3..10b8aaca0e 100644
+index c834fea5d3..0b7829c736 100644
 --- a/src/mainboard/dell/optiplex_9020/mainboard.c
 +++ b/src/mainboard/dell/optiplex_9020/mainboard.c
 @@ -1,7 +1,12 @@
@@ -130,18 +130,19 @@ index c834fea5d3..10b8aaca0e 100644
  #include <device/device.h>
  #include <drivers/intel/gma/int15.h>
 +#include <option.h>
-+#include <southbridge/intel/lynxpoint/lp_gpio.h>
++#include <southbridge/intel/common/gpio.h>
 +#include "sch5555_ec.h"
  
  static void mainboard_enable(struct device *dev)
  {
-@@ -13,3 +18,380 @@ static void mainboard_enable(struct device *dev)
+@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev)
  struct chip_operations mainboard_ops = {
  	.enable_dev = mainboard_enable,
  };
 +
-+#define HWM_TAB_ADD_TEMP_TARGET 1
++#define HWM_TAB_ADD_TEMP_TARGET	1
 +#define HWM_TAB_PKG_POWER_ANY	0xffff
++#define CHASSIS_TYPE_UNKNOWN	0xff
 +
 +struct hwm_tab_entry {
 +	uint16_t addr;
@@ -390,7 +391,7 @@ index c834fea5d3..10b8aaca0e 100644
 +
 +	// Read chassis type from GPIO
 +	gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
-+			    get_gpio(17) << 1 | get_gpio(0);
++			    get_gpio(17) << 1 | get_gpio(1);
 +
 +	printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
 +
@@ -408,7 +409,7 @@ index c834fea5d3..10b8aaca0e 100644
 +	case 0x0f:
 +		return 6;
 +	default:
-+		die("Unknown GPIO chassis type\n");
++		return CHASSIS_TYPE_UNKNOWN;
 +	}
 +
 +}
@@ -469,9 +470,15 @@ index c834fea5d3..10b8aaca0e 100644
 +	ec_write(1, 0x2fc, 0xa0);
 +	ec_write(1, 0x2fd, 0x32);
 +
-+	// Apply HWM table based on chassis type
 +	chassis_type = get_chassis_type();
-+	printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type);
++
++	if (chassis_type != CHASSIS_TYPE_UNKNOWN) {
++		printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type);
++	} else {
++		printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n");
++	}
++
++	// Apply HWM table based on chassis type
 +	switch (chassis_type) {
 +	case 3:
 +		apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3));
@@ -485,19 +492,17 @@ index c834fea5d3..10b8aaca0e 100644
 +	case 6:
 +		apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6));
 +		break;
-+	default:
-+		die("Unknown chassis type\n");
 +	}
 +
-+	if (CONFIG_MAX_CPUS > 2) {
-+		ec_write(1, 0x9e, 0x30);
-+		ec_write(1, 0xeb, ec_read(1, 0xea));
-+	}
++	// NOTE: vendor firmware applies these when "max core address" > 2
++	// i think this is always the case
++	ec_write(1, 0x9e, 0x30);
++	ec_write(1, 0xeb, ec_read(1, 0xea));
 +
 +	ec_write(1, 0x2fc, saved_2fc);
 +
-+	// Apply full speed fan config if requested
-+	if (get_uint_option("fan_full_speed", 0)) {
++	// Apply full speed fan config if requested or if the chassis type is unknown
++	if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) {
 +		printk(BIOS_DEBUG, "Setting full fan speed\n");
 +		ec_write(1, 0x80, 0x60 | ec_read(1, 0x80));
 +		ec_write(1, 0x81, 0x60 | ec_read(1, 0x81));
@@ -518,7 +523,7 @@ index c834fea5d3..10b8aaca0e 100644
 +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL);
 diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
 new file mode 100644
-index 0000000000..92244da9ab
+index 0000000000..a1067ac063
 --- /dev/null
 +++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
 @@ -0,0 +1,54 @@
@@ -546,7 +551,7 @@ index 0000000000..92244da9ab
 +	outb(1, SCH555x_EMI_IOBASE);
 +
 +	// wait for ack
-+	for (size_t timeout = 0; timeout < 0xfff; ++timeout)
++	for (size_t retry = 0; retry < 0xfff; ++retry)
 +		if (inb(SCH555x_EMI_IOBASE + 1) & 1)
 +			break;
 +
@@ -572,23 +577,26 @@ index 0000000000..92244da9ab
 +	outb(1, SCH555x_EMI_IOBASE);
 +
 +	// wait for ack
-+	for (size_t timeout = 0; timeout < 0xfff; ++timeout)
++	for (size_t retry = 0; retry < 0xfff; ++retry)
 +		if (inb(SCH555x_EMI_IOBASE + 1) & 1)
 +			break;
 +}
 diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
 new file mode 100644
-index 0000000000..6e703ff865
+index 0000000000..7e399e8e74
 --- /dev/null
 +++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
-@@ -0,0 +1,7 @@
+@@ -0,0 +1,10 @@
 +/* SPDX-License-Identifier: GPL-2.0-only */
 +
-+#pragma once
++#ifndef __SCH5555_EC_H__
++#define __SCH5555_EC_H__
 +
 +uint8_t ec_read(uint8_t addr1, uint16_t addr2);
 +
 +void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val);
++
++#endif
 -- 
 2.39.2
 

config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch

@@ -0,0 +1,49 @@
+From cd3c553a313a26494e5dc31ff8323c3a919f190a Mon Sep 17 00:00:00 2001
+From: Mate Kukri <kukri.mate@gmail.com>
+Date: Wed, 10 Apr 2024 20:31:35 +0100
+Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device
+
+These machines come with a TPM1.2 device by default. It is somewhat
+obsolete these days, but there is no harm in enabling it.
+
+Change-Id: Iec05321862aed58695c256b00494e5953219786d
+Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827
+Reviewed-by: Angel Pons <th3fanbus@gmail.com>
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+---
+ src/mainboard/dell/optiplex_9020/Kconfig       | 2 ++
+ src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
+index 774a72f161..296938aa8d 100644
+--- a/src/mainboard/dell/optiplex_9020/Kconfig
++++ b/src/mainboard/dell/optiplex_9020/Kconfig
+@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select INTEL_GMA_HAVE_VBT
+ 	select INTEL_INT15
+ 	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_HAS_TPM1
+ 	select MAINBOARD_USES_IFD_GBE_REGION
++	select MEMORY_MAPPED_TPM
+ 	select NORTHBRIDGE_INTEL_HASWELL
+ 	select SERIRQ_CONTINUOUS_MODE
+ 	select SOUTHBRIDGE_INTEL_LYNXPOINT
+diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
+index 7bfa6736a6..e5cbd64127 100644
+--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
+@@ -70,6 +70,9 @@ chip northbridge/intel/haswell
+ 					device pnp 2e.b  off end	# Floppy Controller
+ 					device pnp 2e.11 off end	# Parallel Port
+ 				end
++				chip drivers/pc80/tpm
++					device pnp 0c31.0 on end
++				end
+ 			end
+ 			device pci 1f.2 on  end				# SATA controller 1
+ 			device pci 1f.3 on  end				# SMBus
+-- 
+2.39.2
+

config/coreboot/default/patches/0058-haswell-NRI-include-commonlib-bsd-clamp.h.patch

@@ -1,109 +0,0 @@
-From 0310d8b3fcf8f305f655dacc3322de60bdc2adc4 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Mon, 8 Apr 2024 00:38:18 +0100
-Subject: [PATCH 1/1] haswell NRI: include commonlib/bsd/clamp.h
-
-the location of clamp.h changed. these sources were rebased
-from an older coreboot revision. update to match new code.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/northbridge/intel/haswell/native_raminit/change_margin.c   | 2 +-
- src/northbridge/intel/haswell/native_raminit/configure_mc.c    | 2 +-
- src/northbridge/intel/haswell/native_raminit/init_mpll.c       | 2 +-
- src/northbridge/intel/haswell/native_raminit/io_comp_control.c | 2 +-
- src/northbridge/intel/haswell/native_raminit/lookup_timings.c  | 2 +-
- src/northbridge/intel/haswell/native_raminit/timings_refresh.c | 2 +-
- src/northbridge/intel/haswell/native_raminit/train_read_mpr.c  | 2 +-
- 7 files changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
-index 4ba9cfa5c6..299c44a6b0 100644
---- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
-+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
-@@ -1,7 +1,7 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
- #include <assert.h>
--#include <commonlib/clamp.h>
-+#include <commonlib/bsd/clamp.h>
- #include <console/console.h>
- #include <delay.h>
- #include <northbridge/intel/haswell/haswell.h>
-diff --git a/src/northbridge/intel/haswell/native_raminit/configure_mc.c b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
-index 2a667b075b..003fa0e941 100644
---- a/src/northbridge/intel/haswell/native_raminit/configure_mc.c
-+++ b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
-@@ -1,7 +1,7 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
- #include <assert.h>
--#include <commonlib/clamp.h>
-+#include <commonlib/bsd/clamp.h>
- #include <console/console.h>
- #include <delay.h>
- #include <lib.h>
-diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
-index 2faa183724..1f3f2c29a9 100644
---- a/src/northbridge/intel/haswell/native_raminit/init_mpll.c
-+++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
-@@ -1,6 +1,6 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
--#include <commonlib/clamp.h>
-+#include <commonlib/bsd/clamp.h>
- #include <console/console.h>
- #include <delay.h>
- #include <device/pci_ops.h>
-diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
-index ad8c848e57..8a55fd81b2 100644
---- a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
-+++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
-@@ -1,6 +1,6 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
--#include <commonlib/clamp.h>
-+#include <commonlib/bsd/clamp.h>
- #include <console/console.h>
- #include <northbridge/intel/haswell/haswell.h>
- #include <timer.h>
-diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
-index afe2c615d2..b8d6c1ef40 100644
---- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
-+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
-@@ -1,6 +1,6 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
--#include <commonlib/clamp.h>
-+#include <commonlib/bsd/clamp.h>
- #include <types.h>
- 
- #include "raminit_native.h"
-diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
-index 20a05b359b..820bb336b0 100644
---- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
-+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
-@@ -1,7 +1,7 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
- #include <assert.h>
--#include <commonlib/clamp.h>
-+#include <commonlib/bsd/clamp.h>
- #include <console/console.h>
- #include <delay.h>
- #include <device/pci_ops.h>
-diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
-index 0225e1a384..86f79942d3 100644
---- a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
-+++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
-@@ -1,6 +1,6 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
--#include <commonlib/clamp.h>
-+#include <commonlib/bsd/clamp.h>
- #include <console/console.h>
- #include <delay.h>
- #include <northbridge/intel/haswell/haswell.h>
--- 
-2.39.2
-

config/coreboot/default/patches/0059-haswell-NRI-mitigate-compiler-warnings.patch

@@ -1,81 +0,0 @@
-From 2728c87b7f792aa8e4db29d4dc3d2d2f71f6dafd Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Mon, 8 Apr 2024 00:54:44 +0100
-Subject: [PATCH 1/1] haswell NRI: mitigate compiler warnings
-
-Random -Werror warnings. I'd rather patch these up
-than disable warnings-as-errors in the code.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- .../intel/haswell/native_raminit/raminit_native.h            | 1 +
- src/northbridge/intel/haswell/native_raminit/reut.c          | 5 +++--
- src/northbridge/intel/haswell/native_raminit/testing_io.c    | 2 +-
- .../intel/haswell/native_raminit/timings_refresh.c           | 2 +-
- 4 files changed, 6 insertions(+), 4 deletions(-)
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 98e39cb76e..76a74d6569 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -397,6 +397,7 @@ static inline void tick_delay(const uint32_t delay)
- 	/* Just perform reads to a random register */
- 	for (uint32_t start = 0; start <= delay; start++)
- 		junk = mchbar_read32(REUT_ERR_DATA_STATUS);
-+	(void)junk; /* mitigate -Werror=unused-but-set-variable */
- }
- 
- /*
-diff --git a/src/northbridge/intel/haswell/native_raminit/reut.c b/src/northbridge/intel/haswell/native_raminit/reut.c
-index c55cdd9c7e..c861528a92 100644
---- a/src/northbridge/intel/haswell/native_raminit/reut.c
-+++ b/src/northbridge/intel/haswell/native_raminit/reut.c
-@@ -153,7 +153,7 @@ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_
- {
- 	/** TODO: Issuing ZQ commands differs for LPDDR **/
- 	if (ctrl->lpddr)
--		die("%s: LPDDR not yet supported in ZQ calibration\n");
-+		die("LPDDR not yet supported in ZQ calibration\n");
- 
- 	uint8_t opcode; /* NOTE: Only used for LPDDR */
- 	uint16_t zq = 0;
-@@ -173,8 +173,9 @@ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_
- 		opcode = 0xc3;
- 		break;
- 	default:
--		die("%s: ZQ type %u is invalid\n", zq_type);
-+		die("ZQ type %u is invalid\n", zq_type);
- 	}
-+	(void)opcode; /* Mitigate -Werror=unused-but-set-variable */
- 
- 	/* ZQCS on single-channel needs a longer delay */
- 	const uint8_t delay = zq_type == ZQ_SHORT && (!ctrl->dpc[0] || !ctrl->dpc[1]) ? 7 : 1;
-diff --git a/src/northbridge/intel/haswell/native_raminit/testing_io.c b/src/northbridge/intel/haswell/native_raminit/testing_io.c
-index 7716fc4285..63ae59c33e 100644
---- a/src/northbridge/intel/haswell/native_raminit/testing_io.c
-+++ b/src/northbridge/intel/haswell/native_raminit/testing_io.c
-@@ -221,7 +221,7 @@ void setup_io_test(
- 	const uint8_t subseq_wait)
- {
- 	if (!chanmask)
--		die("\n%s: invalid chanmask\n", __func__, chanmask);
-+		die("\n%d: invalid chanmask\n", chanmask);
- 
- 	/*
- 	 * Prepare variables needed for both channels.
-diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
-index 820bb336b0..e5d8088912 100644
---- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
-+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
-@@ -189,7 +189,7 @@ static union tc_srftp_reg make_tc_srftp(const struct sysinfo *const ctrl)
- void configure_timings(struct sysinfo *ctrl)
- {
- 	if (ctrl->lpddr)
--		die("%s: Missing support for LPDDR\n");
-+		die("Missing support for LPDDR\n");
- 
- 	const uint8_t odt_stretch = get_odt_stretch(ctrl);
- 	const union tc_bank_reg tc_bank = make_tc_bank(ctrl);
--- 
-2.39.2
-

config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb

@@ -6,7 +6,6 @@
 #
 # General setup
 #
-CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -16,7 +15,7 @@ CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_CCACHE is not set
 # CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
+CONFIG_UTIL_GENPARSER=y
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
@@ -135,20 +134,12 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
 # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
 CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -174,6 +165,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_DEBUG_SMI is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
 CONFIG_HAVE_IFD_BIN=y
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
 CONFIG_TTYS0_BAUD=115200
 CONFIG_D3COLD_SUPPORT=y
@@ -183,6 +176,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -225,6 +219,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xe8000000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -234,7 +229,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
@@ -454,8 +448,11 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
+CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -477,6 +474,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
@@ -510,7 +510,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console

config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode

@@ -6,7 +6,6 @@
 #
 # General setup
 #
-CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -16,7 +15,7 @@ CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_CCACHE is not set
 # CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
+CONFIG_UTIL_GENPARSER=y
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
@@ -133,20 +132,12 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
 # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
 CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -172,6 +163,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_DEBUG_SMI is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
 CONFIG_HAVE_IFD_BIN=y
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
 CONFIG_TTYS0_BAUD=115200
 CONFIG_D3COLD_SUPPORT=y
@@ -181,6 +174,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -223,6 +217,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xe8000000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -232,7 +227,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
@@ -450,9 +444,12 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
+CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -474,6 +471,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
@@ -507,7 +507,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console

config/coreboot/dell9020mt-nri_12mb/target.cfg

@@ -1,4 +1,4 @@
-tree="default"
+tree="haswell"
 xarch="i386-elf"
 payload_seabios="y"
 payload_seabios_withgrub="y"

config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb

@@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
@@ -458,6 +459,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
 # end of Generic Drivers
@@ -481,6 +484,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2

config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode

@@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
@@ -454,6 +455,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
@@ -478,6 +481,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2

config/coreboot/dell9020mt_12mb/target.cfg

@@ -5,3 +5,4 @@ payload_seabios_withgrub="y"
 payload_seabios_grubonly="y"
 payload_memtest="y"
 grub_scan_disk="ahci"
+release="n"

config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb

@@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
@@ -458,6 +459,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
 # end of Generic Drivers
@@ -481,6 +484,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2

config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode

@@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
@@ -454,6 +455,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
@@ -478,6 +481,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2

config/coreboot/dell9020mtbmrc_12mb/target.cfg

@@ -5,3 +5,4 @@ payload_seabios_withgrub="y"
 payload_seabios_grubonly="y"
 payload_memtest="y"
 grub_scan_disk="ahci"
+release="n"

config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb

@@ -6,7 +6,6 @@
 #
 # General setup
 #
-CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -135,20 +134,12 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
 CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -174,6 +165,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_DEBUG_SMI is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF"
 CONFIG_HAVE_IFD_BIN=y
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
 CONFIG_TTYS0_BAUD=115200
 CONFIG_D3COLD_SUPPORT=y
@@ -183,6 +176,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -225,6 +219,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xe8000000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -234,7 +229,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
@@ -454,8 +448,11 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
+CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -477,6 +474,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
@@ -510,7 +510,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console

config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode

@@ -6,7 +6,6 @@
 #
 # General setup
 #
-CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -133,20 +132,12 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
 CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -172,6 +163,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_DEBUG_SMI is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF"
 CONFIG_HAVE_IFD_BIN=y
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
 CONFIG_TTYS0_BAUD=115200
 CONFIG_D3COLD_SUPPORT=y
@@ -181,6 +174,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 CONFIG_DRIVERS_UART_8250IO=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -223,6 +217,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xe8000000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -232,7 +227,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
@@ -450,9 +444,12 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
+CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -474,6 +471,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
@@ -507,7 +507,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console

config/coreboot/dell9020sff-nri_12mb/target.cfg

@@ -1,4 +1,4 @@
-tree="default"
+tree="haswell"
 xarch="i386-elf"
 payload_seabios="y"
 payload_seabios_withgrub="y"

config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb

@@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
@@ -458,6 +459,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
 # end of Generic Drivers
@@ -481,6 +484,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2

config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode

@@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
@@ -454,6 +455,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
@@ -478,6 +481,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2

config/coreboot/dell9020sff_12mb/target.cfg

@@ -5,3 +5,4 @@ payload_seabios_withgrub="y"
 payload_seabios_grubonly="y"
 payload_memtest="y"
 grub_scan_disk="ahci"
+release="n"

config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb

@@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
@@ -458,6 +459,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
 # end of Generic Drivers
@@ -481,6 +484,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2

config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode

@@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_TPM_PIRQ=0x0
 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
@@ -454,6 +455,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_MEMORY_MAPPED_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
@@ -478,6 +481,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
+# CONFIG_TPM1 is not set
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2

config/coreboot/dell9020sffbmrc_12mb/target.cfg

@@ -5,3 +5,4 @@ payload_seabios_withgrub="y"
 payload_seabios_grubonly="y"
 payload_memtest="y"
 grub_scan_disk="ahci"
+release="n"

config/coreboot/haswell/patches/0001-haswell-NRI-Initialise-MPLL.patch

@@ -1,7 +1,7 @@
-From f3c5218c6d7e211c9e8425e5e71cda76a7de1fad Mon Sep 17 00:00:00 2001
+From cce5392f272b0acc493f47f9b5ca3cf90ce901e8 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 14:36:10 +0200
-Subject: [PATCH 01/15] haswell NRI: Initialise MPLL
+Date: Thu, 11 Apr 2024 17:25:07 +0200
+Subject: [PATCH 01/20] haswell NRI: Initialise MPLL
 
 Add code to initialise the MPLL (Memory PLL). The procedure is similar
 to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
@@ -33,13 +33,13 @@ index ebf7abc6ec..c125d84f0b 100644
  romstage-y += spd_bitmunching.c
 diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
 new file mode 100644
-index 0000000000..2faa183724
+index 0000000000..1f3f2c29a9
 --- /dev/null
 +++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
 @@ -0,0 +1,210 @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +
-+#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
 +#include <console/console.h>
 +#include <delay.h>
 +#include <device/pci_ops.h>
@@ -249,13 +249,13 @@ index 0000000000..2faa183724
 +}
 diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
 new file mode 100644
-index 0000000000..7e96c08938
+index 0000000000..d45b608dd3
 --- /dev/null
 +++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
 @@ -0,0 +1,22 @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +
-+#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
 +#include <console/console.h>
 +#include <northbridge/intel/haswell/haswell.h>
 +#include <timer.h>
@@ -276,10 +276,10 @@ index 0000000000..7e96c08938
 +	return RAMINIT_STATUS_POLL_TIMEOUT;
 +}
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index b06330c4eb..09545422c0 100644
+index 19ec5859ac..bf745e943f 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -20,7 +20,8 @@ struct task_entry {
+@@ -19,7 +19,8 @@ struct task_entry {
  };
  
  static const struct task_entry cold_boot[] = {

config/coreboot/haswell/patches/0002-haswell-NRI-Post-process-selected-timings.patch

@@ -1,7 +1,7 @@
-From e344871e519441d1f7bc6891ca1eda911e3e4bf5 Mon Sep 17 00:00:00 2001
+From 42b21fdce8c8bade53d9d86515f88b0665a4c1b1 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 16:29:55 +0200
-Subject: [PATCH 02/15] haswell NRI: Post-process selected timings
+Subject: [PATCH 02/20] haswell NRI: Post-process selected timings
 
 Once the MPLL has been initialised, convert the timings from the SPD to
 be in DCLKs, which is what the hardware expects. In addition, calculate
@@ -31,13 +31,13 @@ index c125d84f0b..2769e0bbb4 100644
  romstage-y += raminit_main.c
 diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
 new file mode 100644
-index 0000000000..038686c844
+index 0000000000..8b81c7c341
 --- /dev/null
 +++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
 @@ -0,0 +1,62 @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +
-+#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
 +#include <types.h>
 +
 +#include "raminit_native.h"
@@ -98,10 +98,10 @@ index 0000000000..038686c844
 +	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
 +}
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 09545422c0..5f2be980d4 100644
+index bf745e943f..2fea658415 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -22,6 +22,7 @@ struct task_entry {
+@@ -21,6 +21,7 @@ struct task_entry {
  static const struct task_entry cold_boot[] = {
  	{ collect_spd_info,                                       true, "PROCSPD",    },
  	{ initialise_mpll,                                        true, "INITMPLL",   },
@@ -137,7 +137,7 @@ index a54581abc7..01e5ed1bd6 100644
 +
  #endif
 diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-index 2dab8504c4..9ba695fb64 100644
+index 2dab8504c4..7d98341a7e 100644
 --- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
 +++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
 @@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl)
@@ -221,7 +221,7 @@ index 2dab8504c4..9ba695fb64 100644
 +	 */
 +
 +	/* tCK is special */
-+	printk(BIOS_DEBUG, "Selected tCK          : %u ns\n", ctrl->tCK / 256);
++	printk(BIOS_DEBUG, "Selected tCK          : %u ps\n", ctrl->tCK * 1000 / 256);
 +
 +	/* Primary timings */
 +	printk(BIOS_DEBUG, "Selected tAA          : %uT\n", ctrl->tAA);

config/coreboot/haswell/patches/0003-haswell-NRI-Configure-initial-MC-settings.patch

@@ -1,7 +1,7 @@
-From 5d39edaa35e2dc5c3bd0e5b2e8bf821f5f6ff90c Mon Sep 17 00:00:00 2001
+From 574f4965976b56f98a825dea71e919fefb2c8547 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 17:22:07 +0200
-Subject: [PATCH 03/15] haswell NRI: Configure initial MC settings
+Subject: [PATCH 03/20] haswell NRI: Configure initial MC settings
 
 Program initial memory controller settings. Many of these values will be
 adjusted later during training.
@@ -38,14 +38,14 @@ index 2769e0bbb4..fc55277a65 100644
 +romstage-y += timings_refresh.c
 diff --git a/src/northbridge/intel/haswell/native_raminit/configure_mc.c b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
 new file mode 100644
-index 0000000000..2a667b075b
+index 0000000000..88249725a7
 --- /dev/null
 +++ b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
 @@ -0,0 +1,822 @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +
 +#include <assert.h>
-+#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
 +#include <console/console.h>
 +#include <delay.h>
 +#include <lib.h>
@@ -131,22 +131,22 @@ index 0000000000..2a667b075b
 +
 +static const uint8_t rxb_trad[2][5][4] = {
 +	{	/* Vdd low */
-+		/*  1067 MHz,     1333 MHz,     1600 MHz,     1867 MHz,     2133 MHz, */
++		/* 1067 MT/s,    1333 MT/s,    1600 MT/s,    1867 MT/s,    2133 MT/s, */
 +		{4, 3, 3, 2}, {4, 4, 3, 2}, {5, 4, 3, 3}, {5, 4, 4, 3}, {5, 4, 4, 3},
 +	},
 +	{	/* Vdd hi */
-+		/*  1067 MHz,     1333 MHz,     1600 MHz,     1867 MHz,     2133 MHz, */
++		/* 1067 MT/s,    1333 MT/s,    1600 MT/s,    1867 MT/s,    2133 MT/s, */
 +		{4, 3, 3, 2}, {4, 4, 3, 2}, {5, 4, 3, 3}, {5, 4, 4, 3}, {4, 4, 3, 3},
 +	},
 +};
 +
 +static const uint8_t rxb_ultx[2][3][4] = {
 +	{	/* Vdd low */
-+		/*  1067 MHz,     1333 MHz,     1600 MHz, */
++		/* 1067 MT/s,    1333 MT/s,    1600 MT/s, */
 +		{5, 6, 6, 5}, {5, 6, 6, 5}, {4, 6, 6, 6},
 +	},
 +	{	/* Vdd hi */
-+		/*  1067 MHz,     1333 MHz,     1600 MHz, */
++		/* 1067 MT/s,    1333 MT/s,    1600 MT/s, */
 +		{7, 6, 6, 5}, {7, 6, 6, 5}, {7, 6, 6, 6},
 +	},
 +};
@@ -277,7 +277,7 @@ index 0000000000..2a667b075b
 +	const int16_t coding[] = {0, -125, -62, -31, 250, 125, 62, 31};
 +	*best_a = 0;
 +	*best_b = 0;
-+	int16_t	best_err = slope;
++	int16_t best_err = slope;
 +	for (uint8_t b = 0; b < ARRAY_SIZE(coding); b++) {
 +		for (uint8_t a = b; a < ARRAY_SIZE(coding); a++) {
 +			int16_t	error = slope - (coding[a] + coding[b]);
@@ -865,10 +865,10 @@ index 0000000000..2a667b075b
 +	return RAMINIT_STATUS_SUCCESS;
 +}
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 5f2be980d4..3a773cfa19 100644
+index 2fea658415..fcc981ad04 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -23,6 +23,7 @@ static const struct task_entry cold_boot[] = {
+@@ -22,6 +22,7 @@ static const struct task_entry cold_boot[] = {
  	{ collect_spd_info,                                       true, "PROCSPD",    },
  	{ initialise_mpll,                                        true, "INITMPLL",   },
  	{ convert_timings,                                        true, "CONVTIM",    },
@@ -876,7 +876,7 @@ index 5f2be980d4..3a773cfa19 100644
  };
  
  /* Return a generic stepping value to make stepping checks simpler */
-@@ -54,6 +55,7 @@ static void initialize_ctrl(struct sysinfo *ctrl)
+@@ -53,6 +54,7 @@ static void initialize_ctrl(struct sysinfo *ctrl)
  
  	ctrl->cpu = cpu_get_cpuid();
  	ctrl->stepping = get_stepping(ctrl->cpu);

config/coreboot/haswell/patches/0004-haswell-NRI-Add-timings-refresh-programming.patch

@@ -1,7 +1,7 @@
-From 136a9f660bda9cb515cbbe1e859bc68e7aa04d92 Mon Sep 17 00:00:00 2001
+From d94843c7c0e25cb6da4040b845556034fdb0e2c3 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 20:59:58 +0200
-Subject: [PATCH 04/15] haswell NRI: Add timings/refresh programming
+Subject: [PATCH 04/20] haswell NRI: Add timings/refresh programming
 
 Program the registers with timing and refresh parameters.
 
@@ -16,7 +16,7 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  5 files changed, 452 insertions(+), 2 deletions(-)
 
 diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
-index 038686c844..afe2c615d2 100644
+index 8b81c7c341..b8d6c1ef40 100644
 --- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
 +++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
 @@ -60,3 +60,105 @@ uint32_t get_tXP(const uint32_t mem_clock_mhz)
@@ -262,14 +262,14 @@ index d11cda4b3d..70487e1640 100644
  	struct __packed {
  		uint32_t enable_cmd_limit :  1; // Bits  0:0
 diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
-index a9d960f31b..20a05b359b 100644
+index a9d960f31b..54fee0121d 100644
 --- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
 +++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
 @@ -1,13 +1,242 @@
  /* SPDX-License-Identifier: GPL-2.0-or-later */
  
 +#include <assert.h>
-+#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
 +#include <console/console.h>
 +#include <delay.h>
 +#include <device/pci_ops.h>
@@ -458,7 +458,7 @@ index a9d960f31b..20a05b359b 100644
  {
 -	/** TODO: Stub **/
 +	if (ctrl->lpddr)
-+		die("%s: Missing support for LPDDR\n");
++		die("%s: Missing support for LPDDR\n", __func__);
 +
 +	const uint8_t odt_stretch = get_odt_stretch(ctrl);
 +	const union tc_bank_reg tc_bank = make_tc_bank(ctrl);

config/coreboot/haswell/patches/0005-haswell-NRI-Program-memory-map.patch

@@ -1,7 +1,7 @@
-From f2f47233a17045d1fb2338ca62ce0b107fbdf765 Mon Sep 17 00:00:00 2001
+From b872fb9fc10d1789989072b8533b797152e6cb54 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 21:24:50 +0200
-Subject: [PATCH 05/15] haswell NRI: Program memory map
+Subject: [PATCH 05/20] haswell NRI: Program memory map
 
 This is very similar to Sandy/Ivy Bridge, except that there's several
 registers to program in GDXCBAR. One of these GDXCBAR registers has a
@@ -222,10 +222,10 @@ index 0000000000..e3aded2b37
 +	return 0;
 +}
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 3a773cfa19..136a8ba989 100644
+index fcc981ad04..559dfc3a4e 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -24,6 +24,7 @@ static const struct task_entry cold_boot[] = {
+@@ -23,6 +23,7 @@ static const struct task_entry cold_boot[] = {
  	{ initialise_mpll,                                        true, "INITMPLL",   },
  	{ convert_timings,                                        true, "CONVTIM",    },
  	{ configure_mc,                                           true, "CONFMC",     },

config/coreboot/haswell/patches/0006-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch

@@ -1,7 +1,7 @@
-From bf6173834e306cec9c1086bc7189f60ddfd956ef Mon Sep 17 00:00:00 2001
+From 1ea9b05694da7ee61d49d9cd2b7e533a98e42321 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 21:49:40 +0200
-Subject: [PATCH 06/15] haswell NRI: Add DDR3 JEDEC reset and init
+Subject: [PATCH 06/20] haswell NRI: Add DDR3 JEDEC reset and init
 
 Implement JEDEC reset and init sequence for DDR3. The MRS commands are
 issued through the REUT (Robust Electrical Unified Testing) hardware.
@@ -14,12 +14,12 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  .../haswell/native_raminit/io_comp_control.c  |  19 ++
  .../haswell/native_raminit/jedec_reset.c      | 120 ++++++++++
  .../haswell/native_raminit/raminit_main.c     |   2 +
- .../haswell/native_raminit/raminit_native.h   | 101 ++++++++
+ .../haswell/native_raminit/raminit_native.h   |  99 ++++++++
  .../haswell/native_raminit/reg_structs.h      | 154 +++++++++++++
  .../intel/haswell/native_raminit/reut.c       | 196 ++++++++++++++++
  .../intel/haswell/registers/mchbar.h          |  21 ++
  src/southbridge/intel/lynxpoint/pch.h         |   2 +
- 10 files changed, 835 insertions(+)
+ 10 files changed, 833 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/ddr3.c
  create mode 100644 src/northbridge/intel/haswell/native_raminit/jedec_reset.c
  create mode 100644 src/northbridge/intel/haswell/native_raminit/reut.c
@@ -267,7 +267,7 @@ index 0000000000..6ddb11488b
 +	return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT);
 +}
 diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
-index 7e96c08938..ad8c848e57 100644
+index d45b608dd3..8a55fd81b2 100644
 --- a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
 +++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
 @@ -8,6 +8,25 @@
@@ -423,10 +423,10 @@ index 0000000000..de0f676758
 +	return status;
 +}
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 136a8ba989..73ff180b8c 100644
+index 559dfc3a4e..94b268468c 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -25,6 +25,7 @@ static const struct task_entry cold_boot[] = {
+@@ -24,6 +24,7 @@ static const struct task_entry cold_boot[] = {
  	{ convert_timings,                                        true, "CONVTIM",    },
  	{ configure_mc,                                           true, "CONFMC",     },
  	{ configure_memory_map,                                   true, "MEMMAP",     },
@@ -434,7 +434,7 @@ index 136a8ba989..73ff180b8c 100644
  };
  
  /* Return a generic stepping value to make stepping checks simpler */
-@@ -58,6 +59,7 @@ static void initialize_ctrl(struct sysinfo *ctrl)
+@@ -57,6 +58,7 @@ static void initialize_ctrl(struct sysinfo *ctrl)
  	ctrl->stepping = get_stepping(ctrl->cpu);
  	ctrl->vdd_mv = is_hsw_ult() ? 1350 : 1500; /** FIXME: Hardcoded, does it matter? **/
  	ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved;
@@ -443,7 +443,7 @@ index 136a8ba989..73ff180b8c 100644
  }
  
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 4763b25e8d..e3cf4254a0 100644
+index 4763b25e8d..4bc2a4955f 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 @@ -27,6 +27,30 @@
@@ -498,25 +498,23 @@ index 4763b25e8d..e3cf4254a0 100644
  	union tc_bank_rank_c_reg tc_bankrank_c[NUM_CHANNELS];
  	union tc_bank_rank_d_reg tc_bankrank_d[NUM_CHANNELS];
 +
-+	uint16_t mr0[NUM_CHANNELS][NUM_SLOTRANKS];
-+	uint16_t mr1[NUM_CHANNELS][NUM_SLOTRANKS];
-+	uint16_t mr2[NUM_CHANNELS][NUM_SLOTRANKS];
-+	uint16_t mr3[NUM_CHANNELS][NUM_SLOTRANKS];
++	uint16_t mr0[NUM_CHANNELS][NUM_SLOTS];
++	uint16_t mr1[NUM_CHANNELS][NUM_SLOTS];
++	uint16_t mr2[NUM_CHANNELS][NUM_SLOTS];
++	uint16_t mr3[NUM_CHANNELS][NUM_SLOTS];
  };
  
  static inline bool is_hsw_ult(void)
-@@ -196,6 +227,55 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl)
+@@ -196,6 +227,53 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl)
  	memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train));
  }
  
 +/* Number of ticks to wait in units of 69.841279 ns (citation needed) */
 +static inline void tick_delay(const uint32_t delay)
 +{
-+	volatile uint32_t junk;
-+
 +	/* Just perform reads to a random register */
 +	for (uint32_t start = 0; start <= delay; start++)
-+		junk = mchbar_read32(REUT_ERR_DATA_STATUS);
++		mchbar_read32(REUT_ERR_DATA_STATUS);
 +}
 +
 +/*
@@ -561,7 +559,7 @@ index 4763b25e8d..e3cf4254a0 100644
  void raminit_main(enum raminit_boot_mode bootmode);
  
  enum raminit_status collect_spd_info(struct sysinfo *ctrl);
-@@ -203,6 +283,7 @@ enum raminit_status initialise_mpll(struct sysinfo *ctrl);
+@@ -203,6 +281,7 @@ enum raminit_status initialise_mpll(struct sysinfo *ctrl);
  enum raminit_status convert_timings(struct sysinfo *ctrl);
  enum raminit_status configure_mc(struct sysinfo *ctrl);
  enum raminit_status configure_memory_map(struct sysinfo *ctrl);
@@ -569,7 +567,7 @@ index 4763b25e8d..e3cf4254a0 100644
  
  void configure_timings(struct sysinfo *ctrl);
  void configure_refresh(struct sysinfo *ctrl);
-@@ -215,8 +296,28 @@ uint32_t get_tXS_offset(uint32_t mem_clock_mhz);
+@@ -215,8 +294,28 @@ uint32_t get_tXS_offset(uint32_t mem_clock_mhz);
  uint32_t get_tZQOPER(uint32_t mem_clock_mhz, bool lpddr);
  uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr);
  
@@ -779,7 +777,7 @@ index 70487e1640..9929f617fe 100644
  	struct __packed {
 diff --git a/src/northbridge/intel/haswell/native_raminit/reut.c b/src/northbridge/intel/haswell/native_raminit/reut.c
 new file mode 100644
-index 0000000000..c55cdd9c7e
+index 0000000000..31019f74a1
 --- /dev/null
 +++ b/src/northbridge/intel/haswell/native_raminit/reut.c
 @@ -0,0 +1,196 @@
@@ -938,9 +936,9 @@ index 0000000000..c55cdd9c7e
 +{
 +	/** TODO: Issuing ZQ commands differs for LPDDR **/
 +	if (ctrl->lpddr)
-+		die("%s: LPDDR not yet supported in ZQ calibration\n");
++		die("%s: LPDDR not yet supported in ZQ calibration\n", __func__);
 +
-+	uint8_t opcode; /* NOTE: Only used for LPDDR */
++	__maybe_unused uint8_t opcode; /* NOTE: Only used for LPDDR */
 +	uint16_t zq = 0;
 +	switch (zq_type) {
 +	case ZQ_INIT:
@@ -958,7 +956,7 @@ index 0000000000..c55cdd9c7e
 +		opcode = 0xc3;
 +		break;
 +	default:
-+		die("%s: ZQ type %u is invalid\n", zq_type);
++		die("%s: ZQ type %u is invalid\n", __func__, zq_type);
 +	}
 +
 +	/* ZQCS on single-channel needs a longer delay */

config/coreboot/haswell/patches/0007-haswell-NRI-Add-pre-training-steps.patch

@@ -1,7 +1,7 @@
-From 1992c1119e36e7cdbfb676dc167157b0df22f7a4 Mon Sep 17 00:00:00 2001
+From 936d432822fcd9aa2f018444cdc89e48e6d257d5 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sat, 7 May 2022 23:12:18 +0200
-Subject: [PATCH 07/15] haswell NRI: Add pre-training steps
+Subject: [PATCH 07/20] haswell NRI: Add pre-training steps
 
 Implement pre-training steps, which consist of enabling ECC I/O and
 filling the WDB (Write Data Buffer, stores test patterns) through a
@@ -11,12 +11,12 @@ Change-Id: Ie2e09e3b218c4569ed8de5c5e1b05d491032e0f1
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
  .../intel/haswell/native_raminit/Makefile.mk  |   1 +
- .../haswell/native_raminit/raminit_main.c     |  34 ++++
+ .../haswell/native_raminit/raminit_main.c     |  35 ++++
  .../haswell/native_raminit/raminit_native.h   |  24 +++
  .../haswell/native_raminit/reg_structs.h      |  45 +++++
  .../intel/haswell/native_raminit/setup_wdb.c  | 159 ++++++++++++++++++
  .../intel/haswell/registers/mchbar.h          |   9 +
- 6 files changed, 272 insertions(+)
+ 6 files changed, 273 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/setup_wdb.c
 
 diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -31,10 +31,18 @@ index e9212df9e6..8d7d4e4db0 100644
  romstage-y += spd_bitmunching.c
  romstage-y += timings_refresh.c
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 73ff180b8c..5e4674957d 100644
+index 94b268468c..5e4674957d 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -13,6 +13,39 @@
+@@ -3,6 +3,7 @@
+ #include <assert.h>
+ #include <console/console.h>
+ #include <cpu/intel/haswell/haswell.h>
++#include <delay.h>
+ #include <device/pci_ops.h>
+ #include <northbridge/intel/haswell/chip.h>
+ #include <northbridge/intel/haswell/haswell.h>
+@@ -12,6 +13,39 @@
  
  #include "raminit_native.h"
  
@@ -74,7 +82,7 @@ index 73ff180b8c..5e4674957d 100644
  struct task_entry {
  	enum raminit_status (*task)(struct sysinfo *);
  	bool is_enabled;
-@@ -26,6 +59,7 @@ static const struct task_entry cold_boot[] = {
+@@ -25,6 +59,7 @@ static const struct task_entry cold_boot[] = {
  	{ configure_mc,                                           true, "CONFMC",     },
  	{ configure_memory_map,                                   true, "MEMMAP",     },
  	{ do_jedec_init,                                          true, "JEDECINIT",  },
@@ -83,7 +91,7 @@ index 73ff180b8c..5e4674957d 100644
  
  /* Return a generic stepping value to make stepping checks simpler */
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index e3cf4254a0..f29c2ec366 100644
+index 4bc2a4955f..1971b44b66 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 @@ -35,6 +35,13 @@
@@ -100,7 +108,7 @@ index e3cf4254a0..f29c2ec366 100644
  /* ZQ calibration types */
  enum {
  	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
-@@ -318,6 +325,23 @@ void reut_issue_mrs_all(
+@@ -316,6 +323,23 @@ void reut_issue_mrs_all(
  
  enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type);
  

config/coreboot/haswell/patches/0008-haswell-NRI-Add-REUT-I-O-test-library.patch

@@ -1,7 +1,7 @@
-From 9427dcddf5d8ee60c8d272344f10fb440dbd45dd Mon Sep 17 00:00:00 2001
+From 49a7ef2401922a8492ba577a43235bcfba7ea822 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 00:11:29 +0200
-Subject: [PATCH 08/15] haswell NRI: Add REUT I/O test library
+Subject: [PATCH 08/20] haswell NRI: Add REUT I/O test library
 
 Implement a library to run I/O tests using the REUT hardware.
 
@@ -11,9 +11,9 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/raminit_native.h   | 110 +++
  .../haswell/native_raminit/reg_structs.h      | 121 +++
- .../intel/haswell/native_raminit/testing_io.c | 742 ++++++++++++++++++
+ .../intel/haswell/native_raminit/testing_io.c | 744 ++++++++++++++++++
  .../intel/haswell/registers/mchbar.h          |  30 +
- 5 files changed, 1004 insertions(+)
+ 5 files changed, 1006 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/testing_io.c
 
 diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -27,7 +27,7 @@ index 8d7d4e4db0..6e1b365602 100644
 +romstage-y += testing_io.c
  romstage-y += timings_refresh.c
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index f29c2ec366..56df36ca8d 100644
+index 1971b44b66..7f19fde4cc 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 @@ -58,6 +58,88 @@ enum {
@@ -120,9 +120,9 @@ index f29c2ec366..56df36ca8d 100644
  	CT_ITERATION_CLOCK = 0,
  	CT_ITERATION_CMD_NORTH,
 @@ -199,6 +281,10 @@ struct sysinfo {
- 	uint16_t mr1[NUM_CHANNELS][NUM_SLOTRANKS];
- 	uint16_t mr2[NUM_CHANNELS][NUM_SLOTRANKS];
- 	uint16_t mr3[NUM_CHANNELS][NUM_SLOTRANKS];
+ 	uint16_t mr1[NUM_CHANNELS][NUM_SLOTS];
+ 	uint16_t mr2[NUM_CHANNELS][NUM_SLOTS];
+ 	uint16_t mr3[NUM_CHANNELS][NUM_SLOTS];
 +
 +	uint8_t dq_pat;
 +
@@ -130,7 +130,7 @@ index f29c2ec366..56df36ca8d 100644
  };
  
  static inline bool is_hsw_ult(void)
-@@ -342,6 +428,30 @@ void write_wdb_va_pat(
+@@ -340,6 +426,30 @@ void write_wdb_va_pat(
  void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup);
  void setup_wdb(const struct sysinfo *ctrl);
  
@@ -309,10 +309,10 @@ index 7aa8d8c8b2..b943259b91 100644
  		uint32_t start_test    :  1; // Bits  0:0
 diff --git a/src/northbridge/intel/haswell/native_raminit/testing_io.c b/src/northbridge/intel/haswell/native_raminit/testing_io.c
 new file mode 100644
-index 0000000000..7716fc4285
+index 0000000000..2632c238f8
 --- /dev/null
 +++ b/src/northbridge/intel/haswell/native_raminit/testing_io.c
-@@ -0,0 +1,742 @@
+@@ -0,0 +1,744 @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +
 +#include <console/console.h>
@@ -535,8 +535,10 @@ index 0000000000..7716fc4285
 +	const uint8_t en_cadb,
 +	const uint8_t subseq_wait)
 +{
-+	if (!chanmask)
-+		die("\n%s: invalid chanmask\n", __func__, chanmask);
++	if (!chanmask) {
++		printk(BIOS_ERR, "\n%s: chanmask is invalid\n", __func__);
++		return;
++	}
 +
 +	/*
 +	 * Prepare variables needed for both channels.

config/coreboot/haswell/patches/0009-haswell-NRI-Add-range-tracking-library.patch

@@ -1,7 +1,7 @@
-From 3cd11e7e31e0416ead9782213d582aefc6461e94 Mon Sep 17 00:00:00 2001
+From 7f5c3f8c6c8960d1c374b9c95821c19f230fa34f Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 00:56:00 +0200
-Subject: [PATCH 09/15] haswell NRI: Add range tracking library
+Subject: [PATCH 09/20] haswell NRI: Add range tracking library
 
 Implement a small library used to keep track of passing ranges. This
 will be used by 1D training algorithms when margining some parameter.

config/coreboot/haswell/patches/0010-haswell-NRI-Add-library-to-change-margins.patch

@@ -1,7 +1,7 @@
-From 9d416f00d53bda9f074b9f843fef4a6d4537202a Mon Sep 17 00:00:00 2001
+From 8ad18cc335f60a78f47ab9e5a7994f6075b6a176 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 01:11:03 +0200
-Subject: [PATCH 10/15] haswell NRI: Add library to change margins
+Subject: [PATCH 10/20] haswell NRI: Add library to change margins
 
 Implement a library to change Rx/Tx margins. It will be expanded later.
 
@@ -28,13 +28,13 @@ index 2da950771d..ebe9e9b762 100644
  romstage-y += jedec_reset.c
 diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
 new file mode 100644
-index 0000000000..12da59580f
+index 0000000000..055c666eee
 --- /dev/null
 +++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
 @@ -0,0 +1,154 @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +
-+#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
 +#include <console/console.h>
 +#include <delay.h>
 +#include <northbridge/intel/haswell/haswell.h>
@@ -187,7 +187,7 @@ index 0000000000..12da59580f
 +	mchbar_write32(reg, ddr_data_control_0.raw);
 +}
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 56df36ca8d..7c1a786780 100644
+index 7f19fde4cc..906b3143b9 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 @@ -117,6 +117,30 @@ enum test_stop {
@@ -221,7 +221,7 @@ index 56df36ca8d..7c1a786780 100644
  struct wdb_pat {
  	uint32_t start_ptr;	/* Starting pointer in WDB */
  	uint32_t stop_ptr;	/* Stopping pointer in WDB */
-@@ -452,6 +476,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas
+@@ -450,6 +474,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas
  void run_mpr_io_test(bool clear_errors);
  uint8_t run_io_test(struct sysinfo *ctrl, uint8_t chanmask, uint8_t dq_pat, bool clear_errors);
  

config/coreboot/haswell/patches/0011-haswell-NRI-Add-RcvEn-training.patch

@@ -1,7 +1,7 @@
-From 770d4ea91297f76038e9351f4611def640df2137 Mon Sep 17 00:00:00 2001
+From 4254a9ff03658d7a6f1a4e32cfe4c65dbfc072f8 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 00:05:41 +0200
-Subject: [PATCH 11/15] haswell NRI: Add RcvEn training
+Subject: [PATCH 11/20] haswell NRI: Add RcvEn training
 
 Implement the RcvEn (Receive Enable) calibration procedure.
 
@@ -39,7 +39,7 @@ index 5e4674957d..7d444659c3 100644
  
  /* Return a generic stepping value to make stepping checks simpler */
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 7c1a786780..a36ebfacd1 100644
+index 906b3143b9..b4e8c7de5a 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 @@ -42,6 +42,9 @@
@@ -83,7 +83,7 @@ index 7c1a786780..a36ebfacd1 100644
  /* Number of ticks to wait in units of 69.841279 ns (citation needed) */
  static inline void tick_delay(const uint32_t delay)
  {
-@@ -401,6 +414,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
+@@ -399,6 +412,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
  enum raminit_status configure_mc(struct sysinfo *ctrl);
  enum raminit_status configure_memory_map(struct sysinfo *ctrl);
  enum raminit_status do_jedec_init(struct sysinfo *ctrl);

config/coreboot/haswell/patches/0012-haswell-NRI-Add-function-to-change-margins.patch

@@ -1,7 +1,7 @@
-From be7b1c72cff3403ecfd746255fccb80c8cee6403 Mon Sep 17 00:00:00 2001
+From c24b26594bfab47a8709ed7fb5cb77307fb73a53 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 11:58:59 +0200
-Subject: [PATCH 12/15] haswell NRI: Add function to change margins
+Subject: [PATCH 12/20] haswell NRI: Add function to change margins
 
 Implement a function to change margin parameters. Haswell provides a
 register to apply an offset to margin parameters during training, so
@@ -19,14 +19,14 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  4 files changed, 188 insertions(+)
 
 diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
-index 12da59580f..4ba9cfa5c6 100644
+index 055c666eee..299c44a6b0 100644
 --- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
 +++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
 @@ -1,5 +1,6 @@
  /* SPDX-License-Identifier: GPL-2.0-or-later */
  
 +#include <assert.h>
- #include <commonlib/clamp.h>
+ #include <commonlib/bsd/clamp.h>
  #include <console/console.h>
  #include <delay.h>
 @@ -152,3 +153,138 @@ void download_regfile(
@@ -169,7 +169,7 @@ index 12da59580f..4ba9cfa5c6 100644
 +	change_margin(ctrl, param, value0, true, 0, rank, 0, update_ctrl, regfile);
 +}
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index a36ebfacd1..500fc28909 100644
+index b4e8c7de5a..5242b16f28 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 @@ -35,6 +35,18 @@
@@ -206,7 +206,7 @@ index a36ebfacd1..500fc28909 100644
  /* ZQ calibration types */
  enum {
  	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
-@@ -516,6 +536,25 @@ void download_regfile(
+@@ -514,6 +534,25 @@ void download_regfile(
  	bool read_rf_rd,
  	bool read_rf_wr);
  

config/coreboot/haswell/patches/0013-haswell-NRI-Add-read-MPR-training.patch

@@ -1,7 +1,7 @@
-From ec3dd2a40834e363a5ddaef5e8093e1baa1af56e Mon Sep 17 00:00:00 2001
+From e263f0d2e9d6d016d603342651da261bbcb6af1f Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 11:35:49 +0200
-Subject: [PATCH 13/15] haswell NRI: Add read MPR training
+Subject: [PATCH 13/20] haswell NRI: Add read MPR training
 
 Implement read training using DDR3 MPR (Multi-Purpose Register).
 
@@ -11,9 +11,9 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/raminit_main.c     |   1 +
  .../haswell/native_raminit/raminit_native.h   |   4 +
- .../haswell/native_raminit/train_read_mpr.c   | 240 ++++++++++++++++++
+ .../haswell/native_raminit/train_read_mpr.c   | 241 ++++++++++++++++++
  .../intel/haswell/registers/mchbar.h          |   2 +-
- 5 files changed, 247 insertions(+), 1 deletion(-)
+ 5 files changed, 248 insertions(+), 1 deletion(-)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
 
 diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -39,7 +39,7 @@ index 7d444659c3..264d1468f5 100644
  
  /* Return a generic stepping value to make stepping checks simpler */
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 500fc28909..a7551ad63c 100644
+index 5242b16f28..49e9214656 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 @@ -27,6 +27,8 @@
@@ -59,7 +59,7 @@ index 500fc28909..a7551ad63c 100644
  	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
  };
  
-@@ -435,6 +438,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
+@@ -433,6 +436,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
  enum raminit_status configure_memory_map(struct sysinfo *ctrl);
  enum raminit_status do_jedec_init(struct sysinfo *ctrl);
  enum raminit_status train_receive_enable(struct sysinfo *ctrl);
@@ -69,13 +69,13 @@ index 500fc28909..a7551ad63c 100644
  void configure_refresh(struct sysinfo *ctrl);
 diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
 new file mode 100644
-index 0000000000..0225e1a384
+index 0000000000..ade1e36148
 --- /dev/null
 +++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
-@@ -0,0 +1,240 @@
+@@ -0,0 +1,241 @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +
-+#include <commonlib/clamp.h>
++#include <commonlib/bsd/clamp.h>
 +#include <console/console.h>
 +#include <delay.h>
 +#include <northbridge/intel/haswell/haswell.h>
@@ -206,7 +206,8 @@ index 0000000000..0225e1a384
 +		for (dqs_delay = RMPR_START; dqs_delay < RMPR_STOP; dqs_delay += RMPR_STEP) {
 +			printk(RMPR_PLOT, "% 5d", dqs_delay);
 +			const enum regfile_mode regfile = REG_FILE_USE_START;
-+			change_1d_margin_multicast(ctrl, RdT, dqs_delay, 0, false, regfile);
++			/* Looks like MRC uses rank 0 here, but it feels wrong */
++			change_1d_margin_multicast(ctrl, RdT, dqs_delay, rank, false, regfile);
 +			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
 +				if (!rank_in_ch(ctrl, rank, channel))
 +					continue;

config/coreboot/haswell/patches/0014-haswell-NRI-Add-write-leveling.patch

@@ -1,7 +1,7 @@
-From f091b29ba192afe0eb90a737613ec0735c876830 Mon Sep 17 00:00:00 2001
+From bebe0b74bede64b03aa1e3781310ef539465627b Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 12:56:04 +0200
-Subject: [PATCH 14/15] haswell NRI: Add write leveling
+Subject: [PATCH 14/20] haswell NRI: Add write leveling
 
 Implement JEDEC write leveling, which is done in two steps. The first
 step uses the JEDEC procedure to do "fine" write leveling, i.e. align
@@ -14,9 +14,9 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  .../intel/haswell/native_raminit/Makefile.mk  |   1 +
  .../haswell/native_raminit/raminit_main.c     |   1 +
  .../haswell/native_raminit/raminit_native.h   |  10 +
- .../train_jedec_write_leveling.c              | 580 ++++++++++++++++++
+ .../train_jedec_write_leveling.c              | 581 ++++++++++++++++++
  .../intel/haswell/registers/mchbar.h          |   2 +
- 5 files changed, 594 insertions(+)
+ 5 files changed, 595 insertions(+)
  create mode 100644 src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
 
 diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -43,7 +43,7 @@ index 264d1468f5..1ff23be615 100644
  
  /* Return a generic stepping value to make stepping checks simpler */
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index a7551ad63c..666b233c45 100644
+index 49e9214656..86d89f2120 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 @@ -59,6 +59,9 @@
@@ -76,7 +76,7 @@ index a7551ad63c..666b233c45 100644
  /* Number of ticks to wait in units of 69.841279 ns (citation needed) */
  static inline void tick_delay(const uint32_t delay)
  {
-@@ -439,6 +448,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
+@@ -437,6 +446,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
  enum raminit_status do_jedec_init(struct sysinfo *ctrl);
  enum raminit_status train_receive_enable(struct sysinfo *ctrl);
  enum raminit_status train_read_mpr(struct sysinfo *ctrl);
@@ -86,10 +86,10 @@ index a7551ad63c..666b233c45 100644
  void configure_refresh(struct sysinfo *ctrl);
 diff --git a/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
 new file mode 100644
-index 0000000000..1ba28a3bd4
+index 0000000000..ef6483e2bd
 --- /dev/null
 +++ b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
-@@ -0,0 +1,580 @@
+@@ -0,0 +1,581 @@
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +
 +#include <assert.h>
@@ -106,7 +106,8 @@ index 0000000000..1ba28a3bd4
 +
 +static void reset_dram_dll(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
 +{
-+	reut_issue_mrs(ctrl, channel, BIT(rank), 0, ctrl->mr0[channel][rank] | MR0_DLL_RESET);
++	const uint16_t mr0reg = ctrl->mr0[channel][rank / 2];
++	reut_issue_mrs(ctrl, channel, BIT(rank), 0, mr0reg | MR0_DLL_RESET);
 +}
 +
 +static void program_wdb_pattern(struct sysinfo *ctrl, const bool invert)
@@ -463,7 +464,7 @@ index 0000000000..1ba28a3bd4
 +				continue;
 +
 +			/** TODO: Differs for LPDDR **/
-+			uint16_t mr1reg = ctrl->mr1[channel][rank];
++			uint16_t mr1reg = ctrl->mr1[channel][rank / 2];
 +			mr1reg &= ~MR1_QOFF_ENABLE;
 +			mr1reg |= MR1_WL_ENABLE;
 +			if (is_hsw_ult()) {
@@ -605,7 +606,7 @@ index 0000000000..1ba28a3bd4
 +			mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), 0);
 +
 +			/** TODO: Differs for LPDDR **/
-+			const uint16_t mr1reg = ctrl->mr1[channel][rank] | MR1_QOFF_ENABLE;
++			const uint16_t mr1reg = ctrl->mr1[channel][rank / 2] | MR1_QOFF_ENABLE;
 +			reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
 +
 +			printk(BIOS_DEBUG, "\nC%u.R%u:  LftEdge Width\n", channel, rank);

config/coreboot/haswell/patches/0015-haswell-NRI-Add-final-raminit-steps.patch

@@ -1,7 +1,7 @@
-From 94230b02f22d871af5de5c83e2efc6204394475e Mon Sep 17 00:00:00 2001
+From eba8680d618db95028e3f984f25881df0e67abf7 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Sun, 8 May 2022 14:29:05 +0200
-Subject: [PATCH 15/15] haswell NRI: Add final raminit steps
+Subject: [PATCH 15/20] haswell NRI: Add final raminit steps
 
 Implement the remaining raminit steps. Although many training steps are
 missing, this is enough to boot on the Asrock B85M Pro4.
@@ -466,10 +466,10 @@ index 1ff23be615..3a65fb01fb 100644
 -	die("NATIVE RAMINIT: More Magic (tm) required.\n");
  }
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index ffb5e825f0..6bf7e7cdfb 100644
+index 2fed93de5b..5f7ceec222 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -200,8 +200,6 @@ void perform_raminit(const int s3resume)
+@@ -199,8 +199,6 @@ void perform_raminit(const int s3resume)
  		else
  			me_status = ME_INIT_STATUS_SUCCESS;
  
@@ -478,7 +478,7 @@ index ffb5e825f0..6bf7e7cdfb 100644
  		intel_early_me_init_done(me_status);
  	}
  
-@@ -215,7 +213,8 @@ void perform_raminit(const int s3resume)
+@@ -214,7 +212,8 @@ void perform_raminit(const int s3resume)
  	}
  
  	/* Save training data on non-S3 resumes */
@@ -489,10 +489,10 @@ index ffb5e825f0..6bf7e7cdfb 100644
  
  	/** TODO: setup_sdram_meminfo **/
 diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 666b233c45..98e39cb76e 100644
+index 86d89f2120..9bab57b518 100644
 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
 +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -449,6 +449,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+@@ -447,6 +447,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
  enum raminit_status train_receive_enable(struct sysinfo *ctrl);
  enum raminit_status train_read_mpr(struct sysinfo *ctrl);
  enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);

config/coreboot/haswell/patches/0016-Haswell-NRI-Implement-fast-boot-path.patch

@@ -0,0 +1,722 @@
+From c7d6a901edf648f0f02dd2053337bcf3a319e49b Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sat, 13 Apr 2024 01:16:30 +0200
+Subject: [PATCH 16/20] Haswell NRI: Implement fast boot path
+
+When the memory configuration hasn't changed, there is no need to do
+full memory training. Instead, boot firmware can use saved training
+data to reinitialise the memory controller and memory.
+
+Unlike native RAM init for other platforms, Haswell does not save the
+main structure (the "mighty ctrl" struct) to flash. Instead, separate
+structures define the data to be saved, which can be smaller than the
+main structure.
+
+This makes S3 suspend and resume work: RAM contents MUST be preserved
+for a S3 resume to succeed, but RAM training destroys RAM contents.
+
+Change-Id: I06f6cd39ceecdca104fae89159f28e85cf7ff4e6
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/activate_mc.c      |  17 +
+ .../intel/haswell/native_raminit/ddr3.c       |  41 ++
+ .../haswell/native_raminit/raminit_main.c     |  34 +-
+ .../haswell/native_raminit/raminit_native.c   |  30 +-
+ .../haswell/native_raminit/raminit_native.h   |  18 +
+ .../haswell/native_raminit/save_restore.c     | 387 ++++++++++++++++++
+ 7 files changed, 504 insertions(+), 24 deletions(-)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/save_restore.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index d97da72890..8fdd17c542 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -13,6 +13,7 @@ romstage-y += raminit_main.c
+ romstage-y += raminit_native.c
+ romstage-y += ranges.c
+ romstage-y += reut.c
++romstage-y += save_restore.c
+ romstage-y += setup_wdb.c
+ romstage-y += spd_bitmunching.c
+ romstage-y += testing_io.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
+index 78a7ad27ef..0b3eb917da 100644
+--- a/src/northbridge/intel/haswell/native_raminit/activate_mc.c
++++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
+@@ -333,6 +333,23 @@ enum raminit_status activate_mc(struct sysinfo *ctrl)
+ 	return RAMINIT_STATUS_SUCCESS;
+ }
+ 
++enum raminit_status normal_state(struct sysinfo *ctrl)
++{
++	/* Enable periodic COMP */
++	mchbar_write32(M_COMP, (union pcu_comp_reg) {
++		.comp_interval = COMP_INT,
++	}.raw);
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		if (!does_ch_exist(ctrl, channel))
++			continue;
++
++		/* Set MC to normal mode and clean the ODT and CKE */
++		mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12);
++	}
++	power_down_config(ctrl);
++	return RAMINIT_STATUS_SUCCESS;
++}
++
+ static void mc_lockdown(void)
+ {
+ 	/* Lock memory controller registers */
+diff --git a/src/northbridge/intel/haswell/native_raminit/ddr3.c b/src/northbridge/intel/haswell/native_raminit/ddr3.c
+index 6ddb11488b..9b6368edb1 100644
+--- a/src/northbridge/intel/haswell/native_raminit/ddr3.c
++++ b/src/northbridge/intel/haswell/native_raminit/ddr3.c
+@@ -2,6 +2,7 @@
+ 
+ #include <assert.h>
+ #include <console/console.h>
++#include <delay.h>
+ #include <northbridge/intel/haswell/haswell.h>
+ #include <types.h>
+ 
+@@ -215,3 +216,43 @@ enum raminit_status ddr3_jedec_init(struct sysinfo *ctrl)
+ 	ddr3_program_mr0(ctrl, 1);
+ 	return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT);
+ }
++
++enum raminit_status exit_selfrefresh(struct sysinfo *ctrl)
++{
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		if (!does_ch_exist(ctrl, channel))
++			continue;
++
++		/* Fields in ctrl aren't populated on a warm boot */
++		union ddr_data_control_0_reg data_control_0 = {
++			.raw = mchbar_read32(DQ_CONTROL_0(channel, 0)),
++		};
++		data_control_0.read_rf_rd = 1;
++		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
++			if (!rank_in_ch(ctrl, rank, channel))
++				continue;
++
++			data_control_0.read_rf_rank = rank;
++			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
++		}
++	}
++
++	/* Time needed to stabilize the DCLK (~6 us) */
++	udelay(6);
++
++	/* Pull the DIMMs out of self refresh by asserting CKE high */
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		const union reut_misc_cke_ctrl_reg reut_misc_cke_ctrl = {
++			.cke_on = ctrl->rankmap[channel],
++		};
++		mchbar_write32(REUT_ch_MISC_CKE_CTRL(channel), reut_misc_cke_ctrl.raw);
++	}
++	mchbar_write32(REUT_MISC_ODT_CTRL, 0);
++
++	const enum raminit_status status = reut_issue_zq(ctrl, ctrl->chanmap, ZQ_LONG);
++	if (status) {
++		/* ZQCL errors don't seem to be a fatal problem here */
++		printk(BIOS_ERR, "ZQ Long failed during S3 resume or warm reset flow\n");
++	}
++	return RAMINIT_STATUS_SUCCESS;
++}
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index 3a65fb01fb..056dde1adc 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -64,6 +64,22 @@ static const struct task_entry cold_boot[] = {
+ 	{ train_read_mpr,                                         true, "RDMPRT",     },
+ 	{ train_jedec_write_leveling,                             true, "JWRL",       },
+ 	{ activate_mc,                                            true, "ACTIVATE",   },
++	{ save_training_values,                                   true, "SAVE_TRAIN", },
++	{ save_non_training,                                      true, "SAVE_NONT",  },
++	{ raminit_done,                                           true, "RAMINITEND", },
++};
++
++static const struct task_entry fast_boot[] = {
++	{ collect_spd_info,                                       true, "PROCSPD",    },
++	{ restore_non_training,                                   true, "RST_NONT",   },
++	{ initialise_mpll,                                        true, "INITMPLL",   },
++	{ configure_mc,                                           true, "CONFMC",     },
++	{ configure_memory_map,                                   true, "MEMMAP",     },
++	{ do_jedec_init,                                          true, "JEDECINIT",  },
++	{ pre_training,                                           true, "PRETRAIN",   },
++	{ restore_training_values,                                true, "RST_TRAIN",  },
++	{ exit_selfrefresh,                                       true, "EXIT_SR",    },
++	{ normal_state,                                           true, "NORMALMODE", },
+ 	{ raminit_done,                                           true, "RAMINITEND", },
+ };
+ 
+@@ -102,11 +118,11 @@ static void initialize_ctrl(struct sysinfo *ctrl)
+ 	ctrl->bootmode = bootmode;
+ }
+ 
+-static enum raminit_status try_raminit(struct sysinfo *ctrl)
++static enum raminit_status try_raminit(
++	struct sysinfo *ctrl,
++	const struct task_entry *const schedule,
++	const size_t length)
+ {
+-	const struct task_entry *const schedule = cold_boot;
+-	const size_t length = ARRAY_SIZE(cold_boot);
+-
+ 	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
+ 
+ 	for (size_t i = 0; i < length; i++) {
+@@ -140,8 +156,16 @@ void raminit_main(const enum raminit_boot_mode bootmode)
+ 	mighty_ctrl.bootmode = bootmode;
+ 	initialize_ctrl(&mighty_ctrl);
+ 
++	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
++
++	if (bootmode != BOOTMODE_COLD) {
++		status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot));
++		if (status == RAMINIT_STATUS_SUCCESS)
++			return;
++	}
++
+ 	/** TODO: Try more than once **/
+-	enum raminit_status status = try_raminit(&mighty_ctrl);
++	status = try_raminit(&mighty_ctrl, cold_boot, ARRAY_SIZE(cold_boot));
+ 
+ 	if (status != RAMINIT_STATUS_SUCCESS)
+ 		die("Memory initialization was met with utmost failure and misery\n");
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+index 5f7ceec222..3ad8ce29e7 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+@@ -54,23 +54,17 @@ static bool early_init_native(enum raminit_boot_mode bootmode)
+ 	return cpu_replaced;
+ }
+ 
+-#define MRC_CACHE_VERSION 1
+-
+-struct mrc_data {
+-	const void *buffer;
+-	size_t buffer_len;
+-};
+-
+-static void save_mrc_data(struct mrc_data *md)
++static void save_mrc_data(void)
+ {
+-	mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len);
++	mrc_cache_stash_data(MRC_TRAINING_DATA, reg_frame_rev(),
++			     reg_frame_ptr(), reg_frame_size());
+ }
+ 
+ static struct mrc_data prepare_mrc_cache(void)
+ {
+ 	struct mrc_data md = {0};
+ 	md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+-						MRC_CACHE_VERSION,
++						reg_frame_rev(),
+ 						&md.buffer_len);
+ 	return md;
+ }
+@@ -94,14 +88,15 @@ static void raminit_reset(void)
+ }
+ 
+ static enum raminit_boot_mode do_actual_raminit(
+-	struct mrc_data *md,
+ 	const bool s3resume,
+ 	const bool cpu_replaced,
+ 	const enum raminit_boot_mode orig_bootmode)
+ {
++	struct mrc_data md = prepare_mrc_cache();
++
+ 	enum raminit_boot_mode bootmode = orig_bootmode;
+ 
+-	bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/
++	bool save_data_valid = md.buffer && md.buffer_len == reg_frame_size();
+ 
+ 	if (s3resume) {
+ 		if (bootmode == BOOTMODE_COLD) {
+@@ -154,7 +149,7 @@ static enum raminit_boot_mode do_actual_raminit(
+ 	assert(save_data_valid != (bootmode == BOOTMODE_COLD));
+ 	if (save_data_valid) {
+ 		printk(BIOS_INFO, "Using cached memory parameters\n");
+-		die("RAMINIT: Fast boot is not yet implemented\n");
++		memcpy(reg_frame_ptr(), md.buffer, reg_frame_size());
+ 	}
+ 	printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]);
+ 	printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]);
+@@ -181,10 +176,8 @@ void perform_raminit(const int s3resume)
+ 	wait_txt_clear();
+ 	wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
+ 
+-	struct mrc_data md = prepare_mrc_cache();
+-
+ 	const enum raminit_boot_mode bootmode =
+-			do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode);
++			do_actual_raminit(s3resume, cpu_replaced, orig_bootmode);
+ 
+ 	/** TODO: report_memory_config **/
+ 
+@@ -212,9 +205,8 @@ void perform_raminit(const int s3resume)
+ 	}
+ 
+ 	/* Save training data on non-S3 resumes */
+-	/** TODO: Enable this once training data is populated **/
+-	if (0 && !s3resume)
+-		save_mrc_data(&md);
++	if (!s3resume)
++		save_mrc_data();
+ 
+ 	/** TODO: setup_sdram_meminfo **/
+ }
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 9bab57b518..0750904aec 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -169,6 +169,8 @@ enum regfile_mode {
+ 	REG_FILE_USE_CURRENT,	/* Used when changing parameters after the test */
+ };
+ 
++struct register_save_frame;
++
+ struct wdb_pat {
+ 	uint32_t start_ptr;	/* Starting pointer in WDB */
+ 	uint32_t stop_ptr;	/* Stopping pointer in WDB */
+@@ -219,6 +221,7 @@ enum raminit_status {
+ 	RAMINIT_STATUS_RCVEN_FAILURE,
+ 	RAMINIT_STATUS_RMPR_FAILURE,
+ 	RAMINIT_STATUS_JWRL_FAILURE,
++	RAMINIT_STATUS_INVALID_CACHE,
+ 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
+ };
+ 
+@@ -228,6 +231,11 @@ enum generic_stepping {
+ 	STEPPING_C0 = 3,
+ };
+ 
++struct mrc_data {
++	const void *buffer;
++	size_t buffer_len;
++};
++
+ struct raminit_dimm_info {
+ 	spd_raw_data raw_spd;
+ 	struct dimm_attr_ddr3_st data;
+@@ -447,12 +455,22 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+ enum raminit_status train_receive_enable(struct sysinfo *ctrl);
+ enum raminit_status train_read_mpr(struct sysinfo *ctrl);
+ enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
++enum raminit_status save_training_values(struct sysinfo *ctrl);
++enum raminit_status restore_training_values(struct sysinfo *ctrl);
++enum raminit_status save_non_training(struct sysinfo *ctrl);
++enum raminit_status restore_non_training(struct sysinfo *ctrl);
++enum raminit_status exit_selfrefresh(struct sysinfo *ctrl);
++enum raminit_status normal_state(struct sysinfo *ctrl);
+ enum raminit_status activate_mc(struct sysinfo *ctrl);
+ enum raminit_status raminit_done(struct sysinfo *ctrl);
+ 
+ void configure_timings(struct sysinfo *ctrl);
+ void configure_refresh(struct sysinfo *ctrl);
+ 
++struct register_save_frame *reg_frame_ptr(void);
++size_t reg_frame_size(void);
++uint32_t reg_frame_rev(void);
++
+ uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
+ uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
+ uint32_t get_tAONPD(uint32_t mem_clock_mhz);
+diff --git a/src/northbridge/intel/haswell/native_raminit/save_restore.c b/src/northbridge/intel/haswell/native_raminit/save_restore.c
+new file mode 100644
+index 0000000000..f1f50e3ff8
+--- /dev/null
++++ b/src/northbridge/intel/haswell/native_raminit/save_restore.c
+@@ -0,0 +1,387 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <assert.h>
++#include <console/console.h>
++#include <northbridge/intel/haswell/haswell.h>
++#include <types.h>
++
++#include "raminit_native.h"
++
++uint32_t reg_frame_rev(void)
++{
++	/*
++	 * Equivalent to MRC_CACHE_REVISION, but hidden via abstraction.
++	 * The structures that get saved to flash are contained within
++	 * this translation unit, so changes outside this file shouldn't
++	 * require invalidating the cache.
++	 */
++	return 1;
++}
++
++struct register_save {
++	uint16_t lower;
++	uint16_t upper;
++};
++
++/** TODO: Haswell DDRIO aliases writes: 0x80 .. 0xff => 0x00 .. 0x7f **/
++static const struct register_save ddrio_per_byte_list[] = {
++	{0x0000, 0x003c}, /* 16 registers */
++//	{0x0048, 0x0084}, /* 16 registers */	/** TODO: BDW support **/
++	{0x0048, 0x004c}, /*  2 registers */
++	{0x005c, 0x0078}, /*  8 registers */
++};
++#define DDRIO_PER_BYTE_REGISTER_COUNT	(16 + 2 + 8)
++
++static const struct register_save ddrio_per_ch_list[] = {
++	/* CKE */
++	{0x1204, 0x1208}, /* 2 registers */
++	{0x1214, 0x121c}, /* 3 registers */
++	/* CMD North */
++	{0x1404, 0x140c}, /* 3 registers */
++	/* CLK */
++	{0x1808, 0x1810}, /* 3 registers */
++	/* CMD South */
++	{0x1a04, 0x1a0c}, /* 3 registers */
++	/* CTL */
++	{0x1c14, 0x1c1c}, /* 3 registers */
++};
++#define DDRIO_PER_CH_REGISTER_COUNT	(2 + 3 * 5)
++
++static const struct register_save ddrio_common_list[] = {
++	{0x2000, 0x2008}, /* 3 registers */
++	{0x3a14, 0x3a1c}, /* 3 registers */
++	{0x3a24, 0x3a24}, /* 1 registers */
++};
++
++#define DDRIO_COMMON_REGISTER_COUNT	(3 + 3 + 1)
++
++static const struct register_save mcmain_per_ch_list[] = {
++	{0x4000, 0x4014}, /* 6 registers */
++	{0x4024, 0x4028}, /* 2 registers */
++	{0x40d0, 0x40d0}, /* 1 registers */
++	{0x4220, 0x4224}, /* 2 registers */
++	{0x4294, 0x4294}, /* 1 registers */
++	{0x429c, 0x42a0}, /* 2 registers */
++	{0x42ec, 0x42fc}, /* 5 registers */
++	{0x4328, 0x4328}, /* 1 registers */
++	{0x438c, 0x4390}, /* 2 registers */
++};
++#define MCMAIN_PER_CH_REGISTER_COUNT	(6 + 2 + 1 + 2 + 1 + 2 + 5 + 1 + 2)
++
++static const struct register_save misc_common_list[] = {
++	{0x5884, 0x5888}, /*  2 registers */
++	{0x5890, 0x589c}, /*  4 registers */
++	{0x58a4, 0x58a4}, /*  1 registers */
++	{0x58d0, 0x58e4}, /*  6 registers */
++	{0x5880, 0x5880}, /*  1 registers */
++	{0x5000, 0x50dc}, /* 56 registers */
++	{0x59b8, 0x59b8}  /*  1 registers */
++};
++#define MISC_COMMON_REGISTER_COUNT	(2 + 4 + 1 + 6 + 1 + 56 + 1)
++
++struct save_params {
++	bool is_initialised;
++
++	/* Memory base frequency, either 100 or 133 MHz */
++	uint8_t base_freq;
++
++	/* Multiplier */
++	uint32_t multiplier;
++
++	/* Memory clock in MHz */
++	uint32_t mem_clock_mhz;
++
++	/* Memory clock in femtoseconds */
++	uint32_t mem_clock_fs;
++
++	/* Quadrature clock in picoseconds */
++	uint16_t qclkps;
++
++	/* Bitfield of supported CAS latencies */
++	uint16_t cas_supported;
++
++	/* CPUID value */
++	uint32_t cpu;
++
++	/* Cached CPU stepping value */
++	uint8_t stepping;
++
++	uint16_t vdd_mv;
++
++	union dimm_flags_ddr3_st flags;
++
++	/* Except for tCK, everything is stored in DCLKs */
++	uint32_t tCK;
++	uint32_t tAA;
++	uint32_t tWR;
++	uint32_t tRCD;
++	uint32_t tRRD;
++	uint32_t tRP;
++	uint32_t tRAS;
++	uint32_t tRC;
++	uint32_t tRFC;
++	uint32_t tWTR;
++	uint32_t tRTP;
++	uint32_t tFAW;
++	uint32_t tCWL;
++	uint32_t tCMD;
++
++	uint32_t tREFI;
++	uint32_t tXP;
++
++	uint8_t lpddr_cke_rank_map[NUM_CHANNELS];
++
++	struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS];
++
++	uint8_t chanmap;
++
++	uint32_t channel_size_mb[NUM_CHANNELS];
++
++	/* DIMMs per channel */
++	uint8_t dpc[NUM_CHANNELS];
++
++	uint8_t rankmap[NUM_CHANNELS];
++
++	/* Whether a rank is mirrored or not (only rank 1 of each DIMM can be) */
++	uint8_t rank_mirrored[NUM_CHANNELS];
++
++	/*
++	 * FIXME: LPDDR support is incomplete. The largest chunks are missing,
++	 * but some LPDDR-specific variations in algorithms have been handled.
++	 * LPDDR-specific functions have stubs which will halt upon execution.
++	 */
++	bool lpddr;
++
++	uint8_t lanes;
++
++	/* FIXME: ECC support missing */
++	bool is_ecc;
++};
++
++struct register_save_frame {
++	uint32_t ddrio_per_byte[NUM_CHANNELS][NUM_LANES][DDRIO_PER_BYTE_REGISTER_COUNT];
++	uint32_t ddrio_per_ch[NUM_CHANNELS][DDRIO_PER_CH_REGISTER_COUNT];
++	uint32_t ddrio_common[DDRIO_COMMON_REGISTER_COUNT];
++	uint32_t mcmain_per_ch[NUM_CHANNELS][MCMAIN_PER_CH_REGISTER_COUNT];
++	uint32_t misc_common[MISC_COMMON_REGISTER_COUNT];
++	struct save_params params;
++};
++
++struct register_save_frame *reg_frame_ptr(void)
++{
++	/* The chonky register save frame struct, used for fast boot and S3 resume */
++	static struct register_save_frame register_frame = { 0 };
++	return &register_frame;
++}
++
++size_t reg_frame_size(void)
++{
++	return sizeof(struct register_save_frame);
++}
++
++typedef void (*reg_func_t)(const uint16_t offset, uint32_t *const value);
++
++static void save_value(const uint16_t offset, uint32_t *const value)
++{
++	*value = mchbar_read32(offset);
++}
++
++static void restore_value(const uint16_t offset, uint32_t *const value)
++{
++	mchbar_write32(offset, *value);
++}
++
++static void save_restore(
++	uint32_t *reg_frame,
++	const uint16_t g_offset,
++	const struct register_save *reg_save_list,
++	const size_t reg_save_length,
++	reg_func_t handle_reg)
++{
++	for (size_t i = 0; i < reg_save_length; i++) {
++		const struct register_save *entry = &reg_save_list[i];
++		for (uint16_t offset = entry->lower; offset <= entry->upper; offset += 4) {
++			handle_reg(offset + g_offset, reg_frame++);
++		}
++	}
++}
++
++static void save_restore_all(struct register_save_frame *reg_frame, reg_func_t handle_reg)
++{
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		for (uint8_t byte = 0; byte < NUM_LANES; byte++) {
++			const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, byte);
++			save_restore(
++				reg_frame->ddrio_per_byte[channel][byte],
++				g_offset,
++				ddrio_per_byte_list,
++				ARRAY_SIZE(ddrio_per_byte_list),
++				handle_reg);
++		}
++	}
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, 0);
++		save_restore(
++			reg_frame->ddrio_per_ch[channel],
++			g_offset,
++			ddrio_per_ch_list,
++			ARRAY_SIZE(ddrio_per_ch_list),
++			handle_reg);
++	}
++	save_restore(
++		reg_frame->ddrio_common,
++		0,
++		ddrio_common_list,
++		ARRAY_SIZE(ddrio_common_list),
++		handle_reg);
++
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		const uint16_t g_offset = _MCMAIN_C(0, channel);
++		save_restore(
++			reg_frame->mcmain_per_ch[channel],
++			g_offset,
++			mcmain_per_ch_list,
++			ARRAY_SIZE(mcmain_per_ch_list),
++			handle_reg);
++	}
++	save_restore(
++		reg_frame->misc_common,
++		0,
++		misc_common_list,
++		ARRAY_SIZE(misc_common_list),
++		handle_reg);
++}
++
++enum raminit_status save_training_values(struct sysinfo *ctrl)
++{
++	save_restore_all(reg_frame_ptr(), save_value);
++	return RAMINIT_STATUS_SUCCESS;
++}
++
++enum raminit_status restore_training_values(struct sysinfo *ctrl)
++{
++	save_restore_all(reg_frame_ptr(), restore_value);
++	return RAMINIT_STATUS_SUCCESS;
++}
++
++enum raminit_status save_non_training(struct sysinfo *ctrl)
++{
++	struct register_save_frame *reg_frame = reg_frame_ptr();
++	struct save_params *params = &reg_frame->params;
++
++	params->is_initialised = true;
++
++	params->base_freq     = ctrl->base_freq;
++	params->multiplier    = ctrl->multiplier;
++	params->mem_clock_mhz = ctrl->mem_clock_mhz;
++	params->mem_clock_fs  = ctrl->mem_clock_fs;
++	params->qclkps        = ctrl->qclkps;
++	params->cas_supported = ctrl->cas_supported;
++	params->cpu           = ctrl->cpu;
++	params->stepping      = ctrl->stepping;
++	params->vdd_mv        = ctrl->vdd_mv;
++	params->flags         = ctrl->flags;
++
++	params->tCK       = ctrl->tCK;
++	params->tAA       = ctrl->tAA;
++	params->tWR       = ctrl->tWR;
++	params->tRCD      = ctrl->tRCD;
++	params->tRRD      = ctrl->tRRD;
++	params->tRP       = ctrl->tRP;
++	params->tRAS      = ctrl->tRAS;
++	params->tRC       = ctrl->tRC;
++	params->tRFC      = ctrl->tRFC;
++	params->tWTR      = ctrl->tWTR;
++	params->tRTP      = ctrl->tRTP;
++	params->tFAW      = ctrl->tFAW;
++	params->tCWL      = ctrl->tCWL;
++	params->tCMD      = ctrl->tCMD;
++	params->tREFI     = ctrl->tREFI;
++	params->tXP       = ctrl->tXP;
++
++	params->chanmap = ctrl->chanmap;
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		params->lpddr_cke_rank_map[channel] = ctrl->lpddr_cke_rank_map[channel];
++		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++)
++			params->dimms[channel][slot] = ctrl->dimms[channel][slot];
++	}
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		params->dpc[channel] = ctrl->dpc[channel];
++		params->rankmap[channel] = ctrl->rankmap[channel];
++		params->rank_mirrored[channel] = ctrl->rank_mirrored[channel];
++		params->channel_size_mb[channel] = ctrl->channel_size_mb[channel];
++	}
++	params->lpddr = ctrl->lpddr;
++	params->lanes = ctrl->lanes;
++	params->is_ecc = ctrl->is_ecc;
++	return RAMINIT_STATUS_SUCCESS;
++}
++
++#define RAMINIT_COMPARE(_s1, _s2) \
++	((sizeof(_s1) == sizeof(_s2)) && !memcmp(_s1, _s2, sizeof(_s1)))
++
++enum raminit_status restore_non_training(struct sysinfo *ctrl)
++{
++	struct register_save_frame *reg_frame = reg_frame_ptr();
++	struct save_params *params = &reg_frame->params;
++
++	if (!params->is_initialised) {
++		printk(BIOS_WARNING, "Cannot fast boot: saved data is invalid\n");
++		return RAMINIT_STATUS_INVALID_CACHE;
++	}
++
++	if (!RAMINIT_COMPARE(ctrl->dimms, params->dimms)) {
++		printk(BIOS_WARNING, "Cannot fast boot: DIMMs have changed\n");
++		return RAMINIT_STATUS_INVALID_CACHE;
++	}
++
++	if (ctrl->cpu != params->cpu) {
++		printk(BIOS_WARNING, "Cannot fast boot: CPU has changed\n");
++		return RAMINIT_STATUS_INVALID_CACHE;
++	}
++
++	ctrl->base_freq     = params->base_freq;
++	ctrl->multiplier    = params->multiplier;
++	ctrl->mem_clock_mhz = params->mem_clock_mhz;
++	ctrl->mem_clock_fs  = params->mem_clock_fs;
++	ctrl->qclkps        = params->qclkps;
++	ctrl->cas_supported = params->cas_supported;
++	ctrl->cpu           = params->cpu;
++	ctrl->stepping      = params->stepping;
++	ctrl->vdd_mv        = params->vdd_mv;
++	ctrl->flags         = params->flags;
++
++	ctrl->tCK       = params->tCK;
++	ctrl->tAA       = params->tAA;
++	ctrl->tWR       = params->tWR;
++	ctrl->tRCD      = params->tRCD;
++	ctrl->tRRD      = params->tRRD;
++	ctrl->tRP       = params->tRP;
++	ctrl->tRAS      = params->tRAS;
++	ctrl->tRC       = params->tRC;
++	ctrl->tRFC      = params->tRFC;
++	ctrl->tWTR      = params->tWTR;
++	ctrl->tRTP      = params->tRTP;
++	ctrl->tFAW      = params->tFAW;
++	ctrl->tCWL      = params->tCWL;
++	ctrl->tCMD      = params->tCMD;
++	ctrl->tREFI     = params->tREFI;
++	ctrl->tXP       = params->tXP;
++
++	ctrl->chanmap = params->chanmap;
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		ctrl->lpddr_cke_rank_map[channel] = params->lpddr_cke_rank_map[channel];
++		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++)
++			ctrl->dimms[channel][slot] = params->dimms[channel][slot];
++	}
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		ctrl->dpc[channel] = params->dpc[channel];
++		ctrl->rankmap[channel] = params->rankmap[channel];
++		ctrl->rank_mirrored[channel] = params->rank_mirrored[channel];
++		ctrl->channel_size_mb[channel] = params->channel_size_mb[channel];
++	}
++	ctrl->lpddr = params->lpddr;
++	ctrl->lanes = params->lanes;
++	ctrl->is_ecc = params->is_ecc;
++	return RAMINIT_STATUS_SUCCESS;
++}
+-- 
+2.39.2
+

config/coreboot/haswell/patches/0017-haswell-NRI-Do-sense-amplifier-offset-training.patch

@@ -0,0 +1,476 @@
+From be58501141aa97aa544b670e566cd6cf6797c18e Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Wed, 17 Apr 2024 13:20:32 +0200
+Subject: [PATCH 17/20] haswell NRI: Do sense amplifier offset training
+
+Quoting Wikipedia:
+
+  A sense amplifier is a circuit that is used to amplify and detect
+  small signals in electronic systems. It is commonly used in memory
+  circuits, such as dynamic random access memory (DRAM), to read and
+  amplify the weak signals stored in memory cells.
+
+In this case, we're calibrating the sense amplifiers in the memory
+controller. This training procedure uses a magic "sense amp offset
+cancel" mode of the DDRIO to observe the sampled logic levels, and
+sweeps Vref to find the low-high transition for each bit lane. The
+procedure consists of two stages: the first stage centers per-byte
+Vref (to ensure per-bit Vref offsets are as small as possible) and
+the second stage centers per-bit Vref.
+
+Because this procedure uses the "sense amp offset cancel" mode, it
+does not rely on DRAM being trained. It is assumed that the memory
+controller simply makes sense amp output levels observable via the
+`DDR_DATA_TRAIN_FEEDBACK` register and that the memory bus is idle
+during this training step (so the lane voltage is Vdd / 2).
+
+Note: This procedure will need to be adapted for Broadwell because
+it has per-rank per-bit RxVref registers, whereas Haswell only has
+a single per-bit RxVref register for all ranks.
+
+Change-Id: Ia07db68763f90e9701c8a376e01279ada8dbbe07
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/raminit_main.c     |   1 +
+ .../haswell/native_raminit/raminit_native.h   |  12 +
+ .../native_raminit/train_sense_amp_offset.c   | 341 ++++++++++++++++++
+ .../intel/haswell/registers/mchbar.h          |   2 +
+ 5 files changed, 357 insertions(+)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index 8fdd17c542..4bd668a2d6 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -21,3 +21,4 @@ romstage-y += timings_refresh.c
+ romstage-y += train_jedec_write_leveling.c
+ romstage-y += train_read_mpr.c
+ romstage-y += train_receive_enable.c
++romstage-y += train_sense_amp_offset.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index 056dde1adc..ce637e2d03 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = {
+ 	{ configure_memory_map,                                   true, "MEMMAP",     },
+ 	{ do_jedec_init,                                          true, "JEDECINIT",  },
+ 	{ pre_training,                                           true, "PRETRAIN",   },
++	{ train_sense_amp_offset,                                 true, "SOT",        },
+ 	{ train_receive_enable,                                   true, "RCVET",      },
+ 	{ train_read_mpr,                                         true, "RDMPRT",     },
+ 	{ train_jedec_write_leveling,                             true, "JWRL",       },
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 0750904aec..95ccd0a8b3 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -22,6 +22,8 @@
+ #define NUM_LANES		9
+ #define NUM_LANES_NO_ECC	8
+ 
++#define NUM_BITS		8
++
+ #define COMP_INT		10
+ 
+ /* Always use 12 legs for emphasis (not trained) */
+@@ -218,6 +220,7 @@ enum raminit_status {
+ 	RAMINIT_STATUS_MPLL_INIT_FAILURE,
+ 	RAMINIT_STATUS_POLL_TIMEOUT,
+ 	RAMINIT_STATUS_REUT_ERROR,
++	RAMINIT_STATUS_SAMP_OFFSET_FAILURE,
+ 	RAMINIT_STATUS_RCVEN_FAILURE,
+ 	RAMINIT_STATUS_RMPR_FAILURE,
+ 	RAMINIT_STATUS_JWRL_FAILURE,
+@@ -243,6 +246,12 @@ struct raminit_dimm_info {
+ 	bool valid;
+ };
+ 
++struct vref_margin {
++	uint8_t low;
++	uint8_t center;
++	uint8_t high;
++};
++
+ struct sysinfo {
+ 	enum raminit_boot_mode bootmode;
+ 	enum generic_stepping stepping;
+@@ -330,6 +339,8 @@ struct sysinfo {
+ 	uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ 	int8_t  rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ 
++	struct vref_margin rxdqvrefpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
++
+ 	uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
+ 	uint8_t ctl_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
+ 	uint8_t cke_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
+@@ -452,6 +463,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
+ enum raminit_status configure_mc(struct sysinfo *ctrl);
+ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
+ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
++enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl);
+ enum raminit_status train_receive_enable(struct sysinfo *ctrl);
+ enum raminit_status train_read_mpr(struct sysinfo *ctrl);
+ enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+diff --git a/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
+new file mode 100644
+index 0000000000..d4f199fefb
+--- /dev/null
++++ b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
+@@ -0,0 +1,341 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <assert.h>
++#include <commonlib/bsd/clamp.h>
++#include <console/console.h>
++#include <delay.h>
++#include <lib.h>
++#include <types.h>
++
++#include "raminit_native.h"
++
++#define VREF_OFFSET_PLOT	RAM_DEBUG
++#define SAMP_OFFSET_PLOT	RAM_DEBUG
++
++struct vref_train_data {
++	int8_t best_sum;
++	int8_t best_vref;
++	int8_t sum_bits;
++	uint8_t high_mask;
++	uint8_t low_mask;
++};
++
++static enum raminit_status train_vref_offset(struct sysinfo *ctrl)
++{
++	const int8_t vref_start = -15;
++	const int8_t vref_stop  = 15;
++	const struct vref_train_data initial_vref_values = {
++		.best_sum  = -NUM_LANES,
++		.best_vref = 0,
++		.high_mask = 0,
++		.low_mask  = 0xff,
++	};
++	struct vref_train_data vref_data[NUM_CHANNELS][NUM_LANES];
++
++	printk(VREF_OFFSET_PLOT, "Plot of sum_bits across Vref settings\nChannel");
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		if (!does_ch_exist(ctrl, channel))
++			continue;
++
++		printk(VREF_OFFSET_PLOT, "\t%u\t\t", channel);
++	}
++
++	printk(VREF_OFFSET_PLOT, "\nByte");
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		if (!does_ch_exist(ctrl, channel))
++			continue;
++
++		printk(VREF_OFFSET_PLOT, "\t");
++		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
++			printk(VREF_OFFSET_PLOT, "%u ", byte);
++			vref_data[channel][byte] = initial_vref_values;
++			union ddr_data_control_2_reg data_control_2 = {
++				.raw = ctrl->dq_control_2[channel][byte],
++			};
++			data_control_2.force_bias_on = 1;
++			data_control_2.force_rx_on   = 1;
++			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
++		}
++	}
++
++	/* Sweep through Vref settings and find point SampOffset of +/- 7 passes */
++	printk(VREF_OFFSET_PLOT, "\n1/2 Vref");
++	for (int8_t vref = vref_start; vref <= vref_stop; vref++) {
++		printk(VREF_OFFSET_PLOT, "\n% 3d", vref);
++
++		/*
++		 * To perform this test, enable offset cancel mode and enable ODT.
++		 * Check results and update variables. Ideal result is all zeroes.
++		 * Clear offset cancel mode at end of test to write RX_OFFSET_VDQ.
++		 */
++		change_1d_margin_multicast(ctrl, RdV, vref, 0, false, REG_FILE_USE_RANK);
++
++		/* Program settings for Vref and SampOffset = 7 (8 + 7) */
++		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0xffffffff);
++		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++			if (!does_ch_exist(ctrl, channel))
++				continue;
++
++			/* Propagate delay values (without a read command) */
++			union ddr_data_control_0_reg data_control_0 = {
++				.raw = ctrl->dq_control_0[channel],
++			};
++			data_control_0.read_rf_rd      = 1;
++			data_control_0.read_rf_wr      = 0;
++			data_control_0.read_rf_rank    = 0;
++			data_control_0.force_odt_on    = 1;
++			data_control_0.samp_train_mode = 1;
++			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
++			udelay(1);
++			data_control_0.samp_train_mode = 0;
++			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
++			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
++				const uint8_t feedback = get_data_train_feedback(channel, byte);
++				struct vref_train_data *curr_data = &vref_data[channel][byte];
++				curr_data->low_mask &= feedback;
++				curr_data->sum_bits = -popcnt(feedback);
++			}
++		}
++
++		/* Program settings for Vref and SampOffset = -7 (8 - 7) */
++		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0x11111111);
++		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++			if (!does_ch_exist(ctrl, channel))
++				continue;
++
++			/* Propagate delay values (without a read command) */
++			union ddr_data_control_0_reg data_control_0 = {
++				.raw = ctrl->dq_control_0[channel],
++			};
++			data_control_0.read_rf_rd      = 1;
++			data_control_0.read_rf_wr      = 0;
++			data_control_0.read_rf_rank    = 0;
++			data_control_0.force_odt_on    = 1;
++			data_control_0.samp_train_mode = 1;
++			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
++			udelay(1);
++			data_control_0.samp_train_mode = 0;
++			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
++			printk(VREF_OFFSET_PLOT, "\t");
++			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
++				const uint8_t feedback = get_data_train_feedback(channel, byte);
++				struct vref_train_data *curr_data = &vref_data[channel][byte];
++				curr_data->high_mask |= feedback;
++				curr_data->sum_bits += popcnt(feedback);
++				printk(VREF_OFFSET_PLOT, "%d ", curr_data->sum_bits);
++				if (curr_data->sum_bits > curr_data->best_sum) {
++					curr_data->best_sum  = curr_data->sum_bits;
++					curr_data->best_vref = vref;
++					ctrl->rxvref[channel][0][byte] = vref;
++				} else if (curr_data->sum_bits == curr_data->best_sum) {
++					curr_data->best_vref = vref;
++				}
++			}
++		}
++	}
++	printk(BIOS_DEBUG, "\n\nHi-Lo (XOR):");
++	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		if (!does_ch_exist(ctrl, channel))
++			continue;
++
++		printk(BIOS_DEBUG, "\n  C%u:", channel);
++		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
++			struct vref_train_data *const curr_data = &vref_data[channel][byte];
++			const uint8_t bit_xor = curr_data->high_mask ^ curr_data->low_mask;
++			printk(BIOS_DEBUG, "\t0x%02x", bit_xor);
++			if (bit_xor == 0xff)
++				continue;
++
++			/* Report an error if any bit did not change */
++			status = RAMINIT_STATUS_SAMP_OFFSET_FAILURE;
++		}
++	}
++	if (status)
++		printk(BIOS_ERR, "\nUnexpected bit error in Vref offset training\n");
++
++	printk(BIOS_DEBUG, "\n\nRdVref:");
++	change_1d_margin_multicast(ctrl, RdV, 0, 0, false, REG_FILE_USE_RANK);
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		if (!does_ch_exist(ctrl, channel))
++			continue;
++
++		printk(BIOS_DEBUG, "\n  C%u:", channel);
++		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
++			struct vref_train_data *const curr_data = &vref_data[channel][byte];
++			const int8_t vref_width =
++				curr_data->best_vref - ctrl->rxvref[channel][0][byte];
++
++			/*
++			 * Step size for Rx Vref in DATA_OFFSET_TRAIN is about 3.9 mV
++			 * whereas Rx Vref step size in RX_TRAIN_RANK is about 7.8 mV
++			 */
++			int8_t vref = ctrl->rxvref[channel][0][byte] + vref_width / 2;
++			if (vref < 0)
++				vref--;
++			else
++				vref++;
++
++			for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
++				if (!rank_in_ch(ctrl, rank, channel))
++					continue;
++
++				ctrl->rxvref[channel][rank][byte] = vref / 2;
++				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
++			}
++			printk(BIOS_DEBUG, "\t% 4d", ctrl->rxvref[channel][0][byte]);
++		}
++	}
++	printk(BIOS_DEBUG, "\n\n");
++	return status;
++}
++
++/**
++ * LPDDR has an additional bit for DQS per each byte.
++ *
++ * TODO: The DQS value must be written into Data Control 2.
++ */
++#define NUM_OFFSET_TRAIN_BITS	(NUM_BITS + 1)
++
++#define PLOT_CH_SPACE		"  "
++
++struct samp_train_data {
++	uint8_t first_zero;
++	uint8_t last_one;
++};
++
++static void train_samp_offset(struct sysinfo *ctrl)
++{
++	const uint8_t max_train_bits = ctrl->lpddr ? NUM_OFFSET_TRAIN_BITS : NUM_BITS;
++
++	struct samp_train_data samp_data[NUM_CHANNELS][NUM_LANES][NUM_OFFSET_TRAIN_BITS] = {0};
++
++	printk(BIOS_DEBUG, "Channel ");
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		if (!does_ch_exist(ctrl, channel))
++			continue;
++
++		printk(BIOS_DEBUG, "%u ", channel); /* Same length as PLOT_CH_SPACE */
++		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
++			printk(BIOS_DEBUG, "        %s ", ctrl->lpddr ? " " : "");
++	}
++	printk(BIOS_DEBUG, "\nByte    ");
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		if (!does_ch_exist(ctrl, channel))
++			continue;
++
++		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
++			printk(BIOS_DEBUG, "%u       %s ", byte, ctrl->lpddr ? " " : "");
++
++		printk(BIOS_DEBUG, PLOT_CH_SPACE);
++	}
++	printk(SAMP_OFFSET_PLOT, "\nBits    ");
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
++			printk(SAMP_OFFSET_PLOT, "01234567%s ", ctrl->lpddr ? "S" : "");
++
++		printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
++	}
++	printk(SAMP_OFFSET_PLOT, "\n SAmp\n");
++	for (uint8_t samp_offset = 1; samp_offset <= 15; samp_offset++) {
++		printk(SAMP_OFFSET_PLOT, "% 5d\t", samp_offset);
++
++		uint32_t rx_offset_vdq = 0;
++		for (uint8_t bit = 0; bit < NUM_BITS; bit++) {
++			rx_offset_vdq += samp_offset << (4 * bit);
++		}
++		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, rx_offset_vdq);
++		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++			if (!does_ch_exist(ctrl, channel))
++				continue;
++
++			/* Propagate delay values (without a read command) */
++			union ddr_data_control_0_reg data_control_0 = {
++				.raw = ctrl->dq_control_0[channel],
++			};
++			data_control_0.read_rf_rd      = 1;
++			data_control_0.read_rf_wr      = 0;
++			data_control_0.read_rf_rank    = 0;
++			data_control_0.force_odt_on    = 1;
++			data_control_0.samp_train_mode = 1;
++			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
++			udelay(1);
++			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
++				const uint32_t feedback =
++					get_data_train_feedback(channel, byte);
++
++				for (uint8_t bit = 0; bit < max_train_bits; bit++) {
++					struct samp_train_data *const curr_data =
++							&samp_data[channel][byte][bit];
++					const bool result = feedback & BIT(bit);
++					if (result) {
++						curr_data->last_one = samp_offset;
++					} else if (curr_data->first_zero == 0) {
++						curr_data->first_zero = samp_offset;
++					}
++					printk(SAMP_OFFSET_PLOT, result ? "." : "#");
++				}
++				printk(SAMP_OFFSET_PLOT, " ");
++			}
++			printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
++			data_control_0.samp_train_mode = 0;
++			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
++		}
++		printk(SAMP_OFFSET_PLOT, "\n");
++	}
++	printk(BIOS_DEBUG, "\nBitSAmp ");
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		if (!does_ch_exist(ctrl, channel))
++			continue;
++
++		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
++			uint32_t rx_offset_vdq = 0;
++			for (uint8_t bit = 0; bit < max_train_bits; bit++) {
++				struct samp_train_data *const curr_data =
++						&samp_data[channel][byte][bit];
++
++				uint8_t vref = curr_data->first_zero + curr_data->last_one;
++				vref = clamp_u8(0, vref / 2, 15);
++				/*
++				 * Check for saturation conditions to make sure
++				 * we are as close as possible to Vdd/2 (750 mV).
++				 */
++				if (curr_data->first_zero == 0)
++					vref = 15;
++				if (curr_data->last_one == 0)
++					vref = 0;
++
++				ctrl->rxdqvrefpb[channel][0][byte][bit].center = vref;
++				rx_offset_vdq += vref & 0xf << (4 * bit);
++				printk(BIOS_DEBUG, "%x", vref);
++			}
++			mchbar_write32(RX_OFFSET_VDQ(channel, byte), rx_offset_vdq);
++			printk(BIOS_DEBUG, " ");
++			download_regfile(ctrl, channel, 1, 0, REG_FILE_USE_RANK, 0, 1, 0);
++		}
++		printk(BIOS_DEBUG, PLOT_CH_SPACE);
++	}
++	printk(BIOS_DEBUG, "\n");
++}
++
++enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl)
++{
++	printk(BIOS_DEBUG, "Stage 1: Vref offset training\n");
++	const enum raminit_status status = train_vref_offset(ctrl);
++
++	printk(BIOS_DEBUG, "Stage 2: Samp offset training\n");
++	train_samp_offset(ctrl);
++
++	/* Clean up after test */
++	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
++		if (!does_ch_exist(ctrl, channel))
++			continue;
++
++		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
++		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
++			mchbar_write32(DQ_CONTROL_2(channel, byte),
++				ctrl->dq_control_2[channel][byte]);
++	}
++	io_reset();
++	return status;
++}
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index 49a215aa71..1a168a3fc8 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
++++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -18,6 +18,8 @@
+ #define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
+ #define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
+ 
++#define RX_OFFSET_VDQ(ch, byte)			_DDRIO_C_R_B(0x004c, ch, 0, byte)
++
+ #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
+ 
+ #define DQ_CONTROL_1(ch, byte)			_DDRIO_C_R_B(0x0060, ch, 0, byte)
+-- 
+2.39.2
+

config/coreboot/haswell/patches/0018-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -0,0 +1,39 @@
+From c25dcd8ac80598939edffd011df0fd9ba3d8a1a8 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 12 May 2023 19:55:15 -0600
+Subject: [PATCH 18/20] Remove warning for coreboot images built without a
+ payload
+
+I added this in upstream to prevent people from accidentally flashing
+roms without a payload resulting in a no boot situation, but in
+libreboot lbmk handles the payload and thus this warning always comes
+up. This has caused confusion and concern so just patch it out.
+---
+ payloads/Makefile.mk | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
+index a2336aa876..4f1692a873 100644
+--- a/payloads/Makefile.mk
++++ b/payloads/Makefile.mk
+@@ -49,16 +49,5 @@ distclean-payloads:
+ print-repo-info-payloads:
+ 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
+ 
+-ifeq ($(CONFIG_PAYLOAD_NONE),y)
+-show_notices:: warn_no_payload
+-endif
+-
+-warn_no_payload:
+-	printf "\n\t** WARNING **\n"
+-	printf "coreboot has been built without a payload. Writing\n"
+-	printf "a coreboot image without a payload to your board's\n"
+-	printf "flash chip will result in a non-booting system. You\n"
+-	printf "can use cbfstool to add a payload to the image.\n\n"
+-
+ .PHONY: force-payload coreinfo nvramcui
+-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
+-- 
+2.39.2
+

config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch

@@ -0,0 +1,36 @@
+From 081890bab8d454247b6f7e9cb209f46159c45c8b Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 5 Nov 2023 23:19:42 +0000
+Subject: [PATCH 19/20] use mirrorservice.org for gcc downloads
+
+the gnu.org 302 redirect often fails
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 0a0462e2f6..6ae201239d 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -69,11 +69,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
+ # to the jenkins build as well, or the builder won't download it.
+ 
+ # GCC toolchain archive locations
+-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
+-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
+ IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch

@@ -0,0 +1,204 @@
+From 1a4f454e05b613cb080cdd063dd3efb1fdbb748b Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 19 Feb 2023 18:21:43 +0000
+Subject: [PATCH 20/20] util/ifdtool: add --nuke flag (all 0xFF on region)
+
+When this option is used, the region's contents are overwritten
+with all ones (0xFF).
+
+Example:
+
+./ifdtool --nuke gbe coreboot.rom
+./ifdtool --nuke bios coreboot.com
+./ifdtool --nuke me coreboot.com
+
+Rebased since the last revision update in lbmk.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/ifdtool/ifdtool.c | 113 ++++++++++++++++++++++++++++++-----------
+ 1 file changed, 82 insertions(+), 31 deletions(-)
+
+diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
+index 516570e0a3..1638e1710e 100644
+--- a/util/ifdtool/ifdtool.c
++++ b/util/ifdtool/ifdtool.c
+@@ -2143,6 +2143,7 @@ static void print_usage(const char *name)
+ 	       "                                         tgl    - Tiger Lake\n"
+ 	       "                                         wbg    - Wellsburg\n"
+ 	       "   -S | --setpchstrap                    Write a PCH strap\n"
++	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
+ 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
+ 	       "   -v | --version:                       print the version\n"
+ 	       "   -h | --help:                          print this help\n\n"
+@@ -2151,6 +2152,60 @@ static void print_usage(const char *name)
+ 	       "\n");
+ }
+ 
++static int
++get_region_type_string(const char *region_type_string)
++{
++       if (!strcasecmp("Descriptor", region_type_string))
++               return 0;
++       else if (!strcasecmp("BIOS", region_type_string))
++               return 1;
++       else if (!strcasecmp("ME", region_type_string))
++               return 2;
++       else if (!strcasecmp("GbE", region_type_string))
++               return 3;
++       else if (!strcasecmp("Platform Data", region_type_string))
++               return 4;
++       else if (!strcasecmp("Device Exp1", region_type_string))
++               return 5;
++       else if (!strcasecmp("Secondary BIOS", region_type_string))
++               return 6;
++       else if (!strcasecmp("Reserved", region_type_string))
++               return 7;
++       else if (!strcasecmp("EC", region_type_string))
++               return 8;
++       else if (!strcasecmp("Device Exp2", region_type_string))
++               return 9;
++       else if (!strcasecmp("IE", region_type_string))
++               return 10;
++       else if (!strcasecmp("10GbE_0", region_type_string))
++               return 11;
++       else if (!strcasecmp("10GbE_1", region_type_string))
++               return 12;
++       else if (!strcasecmp("PTT", region_type_string))
++               return 15;
++       return -1;
++}
++
++static void
++nuke(const char *filename, char *image, int size, int region_type)
++{
++       int i;
++       struct region region;
++       const struct frba *frba = find_frba(image, size);
++       if (!frba)
++               exit(EXIT_FAILURE);
++
++       region = get_region(frba, region_type);
++       if (region.size > 0) {
++               for (i = region.base; i <= region.limit; i++) {
++                       if ((i + 1) > (size))
++                               break;
++                       image[i] = 0xFF;
++               }
++               write_image(filename, image, size);
++       }
++}
++
+ int main(int argc, char *argv[])
+ {
+ 	int opt, option_index = 0;
+@@ -2158,6 +2213,7 @@ int main(int argc, char *argv[])
+ 	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
+ 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
+ 	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
++	int mode_nuke = 0;
+ 	int mode_gpr0_disable = 0, mode_gpr0_enable = 0;
+ 	char *region_type_string = NULL, *region_fname = NULL;
+ 	const char *layout_fname = NULL;
+@@ -2192,6 +2248,7 @@ int main(int argc, char *argv[])
+ 		{"validate", 0, NULL, 't'},
+ 		{"setpchstrap", 1, NULL, 'S'},
+ 		{"newvalue", 1, NULL, 'V'},
++		{"nuke", 1, NULL, 'N'},
+ 		{0, 0, 0, 0}
+ 	};
+ 
+@@ -2241,35 +2298,8 @@ int main(int argc, char *argv[])
+ 			region_fname++;
+ 			// Descriptor, BIOS, ME, GbE, Platform
+ 			// valid type?
+-			if (!strcasecmp("Descriptor", region_type_string))
+-				region_type = 0;
+-			else if (!strcasecmp("BIOS", region_type_string))
+-				region_type = 1;
+-			else if (!strcasecmp("ME", region_type_string))
+-				region_type = 2;
+-			else if (!strcasecmp("GbE", region_type_string))
+-				region_type = 3;
+-			else if (!strcasecmp("Platform Data", region_type_string))
+-				region_type = 4;
+-			else if (!strcasecmp("Device Exp1", region_type_string))
+-				region_type = 5;
+-			else if (!strcasecmp("Secondary BIOS", region_type_string))
+-				region_type = 6;
+-			else if (!strcasecmp("Reserved", region_type_string))
+-				region_type = 7;
+-			else if (!strcasecmp("EC", region_type_string))
+-				region_type = 8;
+-			else if (!strcasecmp("Device Exp2", region_type_string))
+-				region_type = 9;
+-			else if (!strcasecmp("IE", region_type_string))
+-				region_type = 10;
+-			else if (!strcasecmp("10GbE_0", region_type_string))
+-				region_type = 11;
+-			else if (!strcasecmp("10GbE_1", region_type_string))
+-				region_type = 12;
+-			else if (!strcasecmp("PTT", region_type_string))
+-				region_type = 15;
+-			if (region_type == -1) {
++			if ((region_type =
++			    get_region_type_string(region_type_string)) == -1) {
+ 				fprintf(stderr, "No such region type: '%s'\n\n",
+ 					region_type_string);
+ 				fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+@@ -2441,6 +2471,22 @@ int main(int argc, char *argv[])
+ 		case 't':
+ 			mode_validate = 1;
+ 			break;
++               case 'N':
++                       region_type_string = strdup(optarg);
++                       if (!region_type_string) {
++                               fprintf(stderr, "No region specified\n");
++                               print_usage(argv[0]);
++                               exit(EXIT_FAILURE);
++                       }
++                       if ((region_type =
++                           get_region_type_string(region_type_string)) == -1) {
++                               fprintf(stderr, "No such region type: '%s'\n\n",
++                                       region_type_string);
++                               print_usage(argv[0]);
++                               exit(EXIT_FAILURE);
++                       }
++                       mode_nuke = 1;
++                       break;
+ 		case 'v':
+ 			print_version();
+ 			exit(EXIT_SUCCESS);
+@@ -2457,7 +2503,7 @@ int main(int argc, char *argv[])
+ 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ 			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
+ 			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
+-			(mode_gpr0_disable | mode_gpr0_enable)) > 1) {
++			(mode_gpr0_disable | mode_gpr0_enable) + mode_nuke) > 1) {
+ 		fprintf(stderr, "You may not specify more than one mode.\n\n");
+ 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ 		exit(EXIT_FAILURE);
+@@ -2466,7 +2512,8 @@ int main(int argc, char *argv[])
+ 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ 			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
+ 			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
+-			mode_validate + (mode_gpr0_disable | mode_gpr0_enable)) == 0) {
++			mode_validate + (mode_gpr0_disable | mode_gpr0_enable) +
++			mode_nuke) == 0) {
+ 		fprintf(stderr, "You need to specify a mode.\n\n");
+ 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ 		exit(EXIT_FAILURE);
+@@ -2576,6 +2623,10 @@ int main(int argc, char *argv[])
+ 		write_image(new_filename, image, size);
+ 	}
+ 
++	if (mode_nuke) {
++		nuke(new_filename, image, size, region_type);
++	}
++
+ 	if (mode_altmedisable) {
+ 		struct fpsba *fpsba = find_fpsba(image, size);
+ 		struct fmsba *fmsba = find_fmsba(image, size);
+-- 
+2.39.2
+

config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch

@@ -0,0 +1,292 @@
+From d97b865a2210e70583e8bf5ee3a73d3c131b29c1 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Sat, 2 Mar 2024 22:51:09 +0000
+Subject: [PATCH 1/4] nb/intel/haswell: make IOMMU a runtime option
+
+When I tested graphics cards on a coreboot port for Dell
+OptiPlex 9020 SFF, I could not use a graphics card unless
+I set iommu=off on the Linux cmdline.
+
+Coreboot's current behaviour is to check whether the CPU
+has vt-d support and, if it does, initialise the IOMMU.
+
+This patch maintains the current behaviour by default, but
+allows the user to turn *off* the IOMMU, even if vt-d is
+supported by the host CPU.
+
+If iommu=Disable is specified, the check will not be
+performed, and the IOMMU will be left disabled. This option
+has been added to all current Haswell boards, though it is
+recommended to leave the IOMMU turned on in most setups.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/mainboard/asrock/b85m_pro4/cmos.default    | 1 +
+ src/mainboard/asrock/b85m_pro4/cmos.layout     | 3 +++
+ src/mainboard/asrock/h81m-hds/cmos.default     | 1 +
+ src/mainboard/asrock/h81m-hds/cmos.layout      | 6 ++++++
+ src/mainboard/dell/optiplex_9020/cmos.default  | 1 +
+ src/mainboard/dell/optiplex_9020/cmos.layout   | 6 ++++++
+ src/mainboard/google/beltino/cmos.layout       | 5 +++++
+ src/mainboard/google/slippy/cmos.layout        | 5 +++++
+ src/mainboard/intel/baskingridge/cmos.layout   | 4 ++++
+ src/mainboard/lenovo/haswell/cmos.default      | 1 +
+ src/mainboard/lenovo/haswell/cmos.layout       | 3 +++
+ src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
+ src/mainboard/supermicro/x10slm-f/cmos.layout  | 6 ++++++
+ src/northbridge/intel/haswell/early_init.c     | 5 +++++
+ 14 files changed, 48 insertions(+)
+
+diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default
+index 01bf20ad16..dfc8b80fb0 100644
+--- a/src/mainboard/asrock/b85m_pro4/cmos.default
++++ b/src/mainboard/asrock/b85m_pro4/cmos.default
+@@ -4,3 +4,4 @@ boot_option=Fallback
+ debug_level=Debug
+ nmi=Enable
+ power_on_after_fail=Disable
++iommu=Enable
+diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout
+index efdc333fc2..c9883ea71d 100644
+--- a/src/mainboard/asrock/b85m_pro4/cmos.layout
++++ b/src/mainboard/asrock/b85m_pro4/cmos.layout
+@@ -11,6 +11,7 @@
+ 	395	4	e	4	debug_level
+ 	408	1	e	1	nmi
+ 	409	2	e	5	power_on_after_fail
++	412	1	e	6	iommu
+ 	984	16	h	0	check_sum
+ # -----------------------------------------------------------------
+ 
+@@ -38,6 +39,8 @@
+ 	5	0	Disable
+ 	5	1	Enable
+ 	5	2	Keep
++	6	0	Disable
++	6	1	Enable
+ # -----------------------------------------------------------------
+ 
+ # -----------------------------------------------------------------
+diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default
+index 01bf20ad16..dfc8b80fb0 100644
+--- a/src/mainboard/asrock/h81m-hds/cmos.default
++++ b/src/mainboard/asrock/h81m-hds/cmos.default
+@@ -4,3 +4,4 @@ boot_option=Fallback
+ debug_level=Debug
+ nmi=Enable
+ power_on_after_fail=Disable
++iommu=Enable
+diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout
+index c9ba76c78f..95ee3d36fb 100644
+--- a/src/mainboard/asrock/h81m-hds/cmos.layout
++++ b/src/mainboard/asrock/h81m-hds/cmos.layout
+@@ -21,6 +21,9 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	5	power_on_after_fail
+ 
++# enable or disable iommu
++412	1	e	6	iommu
++
+ # coreboot config options: check sums
+ 984	16	h	0	check_sum
+ 
+@@ -52,6 +55,9 @@ enumerations
+ 5	1	Enable
+ 5	2	Keep
+ 
++6	0	Disable
++6	1	Enable
++
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
+index cd4046f1ab..c974022472 100644
+--- a/src/mainboard/dell/optiplex_9020/cmos.default
++++ b/src/mainboard/dell/optiplex_9020/cmos.default
+@@ -3,3 +3,4 @@ boot_option=Fallback
+ debug_level=Debug
+ nmi=Disable
+ power_on_after_fail=Disable
++iommu=Enable
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
+index c9ba76c78f..72ff9c4bee 100644
+--- a/src/mainboard/dell/optiplex_9020/cmos.layout
++++ b/src/mainboard/dell/optiplex_9020/cmos.layout
+@@ -21,6 +21,9 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	5	power_on_after_fail
+ 
++# turn iommu on or off
++412	1	e	6	iommu
++
+ # coreboot config options: check sums
+ 984	16	h	0	check_sum
+ 
+@@ -52,6 +55,9 @@ enumerations
+ 5	1	Enable
+ 5	2	Keep
+ 
++6	0	Disable
++6	1	Enable
++
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout
+index 78d44c1415..c143979ae1 100644
+--- a/src/mainboard/google/beltino/cmos.layout
++++ b/src/mainboard/google/beltino/cmos.layout
+@@ -19,6 +19,9 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	7	power_on_after_fail
+ 
++# enable or disable iommu
++412	1	e	8	iommu
++
+ # coreboot config options: bootloader
+ #Used by ChromeOS:
+ 416	128	r	0	vbnv
+@@ -47,6 +50,8 @@ enumerations
+ 7	0	Disable
+ 7	1	Enable
+ 7	2	Keep
++8	0	Disable
++8	1	Enable
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout
+index 78d44c1415..c143979ae1 100644
+--- a/src/mainboard/google/slippy/cmos.layout
++++ b/src/mainboard/google/slippy/cmos.layout
+@@ -19,6 +19,9 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	7	power_on_after_fail
+ 
++# enable or disable iommu
++412	1	e	8	iommu
++
+ # coreboot config options: bootloader
+ #Used by ChromeOS:
+ 416	128	r	0	vbnv
+@@ -47,6 +50,8 @@ enumerations
+ 7	0	Disable
+ 7	1	Enable
+ 7	2	Keep
++8	0	Disable
++8	1	Enable
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout
+index 78d44c1415..f2c602f541 100644
+--- a/src/mainboard/intel/baskingridge/cmos.layout
++++ b/src/mainboard/intel/baskingridge/cmos.layout
+@@ -19,6 +19,8 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	7	power_on_after_fail
+ 
++412	1	e	8	iommu
++
+ # coreboot config options: bootloader
+ #Used by ChromeOS:
+ 416	128	r	0	vbnv
+@@ -47,6 +49,8 @@ enumerations
+ 7	0	Disable
+ 7	1	Enable
+ 7	2	Keep
++8	0	Disable
++8	1	Enable
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default
+index 08db97c5a9..cc6b363cd9 100644
+--- a/src/mainboard/lenovo/haswell/cmos.default
++++ b/src/mainboard/lenovo/haswell/cmos.default
+@@ -14,3 +14,4 @@ trackpoint=Enable
+ backlight=Keyboard
+ enable_dual_graphics=Disable
+ usb_always_on=Disable
++iommu=Enable
+diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout
+index 27915d3ab7..59df76b64c 100644
+--- a/src/mainboard/lenovo/haswell/cmos.layout
++++ b/src/mainboard/lenovo/haswell/cmos.layout
+@@ -23,6 +23,7 @@ entries
+ 
+ # coreboot config options: EC
+ 411	1	e	8	first_battery
++413	1	e	14	iommu
+ 415	1	e	1	wlan
+ 416	1	e	1	trackpoint
+ 417	1	e	1	fn_ctrl_swap
+@@ -72,6 +73,8 @@ enumerations
+ 13	0	Disable
+ 13	1	AC and battery
+ 13	2	AC only
++14	0	Disable
++14	1	Enable
+ 
+ # -----------------------------------------------------------------
+ checksums
+diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default
+index 7ce38fb5d7..6049e7938a 100644
+--- a/src/mainboard/supermicro/x10slm-f/cmos.default
++++ b/src/mainboard/supermicro/x10slm-f/cmos.default
+@@ -5,3 +5,4 @@ debug_level=Debug
+ nmi=Enable
+ power_on_after_fail=Keep
+ hide_ast2400=Disable
++iommu=Enable
+diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout
+index 38ba87aa45..24d39e97ee 100644
+--- a/src/mainboard/supermicro/x10slm-f/cmos.layout
++++ b/src/mainboard/supermicro/x10slm-f/cmos.layout
+@@ -21,6 +21,9 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	5	power_on_after_fail
+ 
++# enable or disable iommu
++412	1	e	6	iommu
++
+ # coreboot config options: mainboard
+ 416	1	e	1	hide_ast2400
+ 
+@@ -55,6 +58,9 @@ enumerations
+ 5	1	Enable
+ 5	2	Keep
+ 
++6	0	Disable
++6	1	Enable
++
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
+index e47deb5da6..1a7e0b1076 100644
+--- a/src/northbridge/intel/haswell/early_init.c
++++ b/src/northbridge/intel/haswell/early_init.c
+@@ -5,6 +5,7 @@
+ #include <device/mmio.h>
+ #include <device/pci_def.h>
+ #include <device/pci_ops.h>
++#include <option.h>
+ 
+ #include "haswell.h"
+ 
+@@ -157,6 +158,10 @@ static void haswell_setup_misc(void)
+ static void haswell_setup_iommu(void)
+ {
+ 	const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
++	u8 enable_iommu = get_uint_option("iommu", 1);
++
++	if (!enable_iommu)
++		return;
+ 
+ 	if (capid0_a & VTD_DISABLE)
+ 		return;
+-- 
+2.39.2
+

config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch

@@ -0,0 +1,29 @@
+From 153ca1a43c2c978fa2b2b82d988b0f838953cfb9 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Sat, 2 Mar 2024 23:00:09 +0000
+Subject: [PATCH 2/4] dell/optiplex_9020: Disable IOMMU by default
+
+Needed to make graphics cards work. Turning it on is
+recommended if only using iGPU, otherwise leave it off
+by default. The IOMMU is extremely buggy when a graphics
+card is used. Leaving it off by default will ensure that
+the default ROM images in Libreboot will work on any setup.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/mainboard/dell/optiplex_9020/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
+index c974022472..a0acd7b6bb 100644
+--- a/src/mainboard/dell/optiplex_9020/cmos.default
++++ b/src/mainboard/dell/optiplex_9020/cmos.default
+@@ -3,4 +3,4 @@ boot_option=Fallback
+ debug_level=Debug
+ nmi=Disable
+ power_on_after_fail=Disable
+-iommu=Enable
++iommu=Disable
+-- 
+2.39.2
+

config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch

@@ -0,0 +1,602 @@
+From 05cc767d1398f91533e87db5ceaa0aabb7918425 Mon Sep 17 00:00:00 2001
+From: Mate Kukri <kukri.mate@gmail.com>
+Date: Thu, 18 Apr 2024 20:28:45 +0100
+Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization
+
+There are 4 different chassis types specified by vendor firmware, each
+with a slightly different HWM configuration.
+
+The chassis type to use is determined at runtime by reading a set of
+4 PCH GPIOs: 70, 38, 17, and 1.
+
+Additionally vendor firmware also provides an option to run the fans at
+full speed. This is substituted with a coreboot nvram option in this
+implementation.
+
+This was tested to make fan control work on my OptiPlex 7020 SFF.
+
+NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
+however the OptiPlex 9020's SCH5555 does not use externally
+programmed EC firmware.
+
+Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
+Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
+---
+ src/mainboard/dell/optiplex_9020/Makefile.mk  |   3 +-
+ src/mainboard/dell/optiplex_9020/bootblock.c  |  25 +-
+ src/mainboard/dell/optiplex_9020/cmos.default |   1 +
+ src/mainboard/dell/optiplex_9020/cmos.layout  |   5 +-
+ src/mainboard/dell/optiplex_9020/mainboard.c  | 387 ++++++++++++++++++
+ src/mainboard/dell/optiplex_9020/sch5555_ec.c |  54 +++
+ src/mainboard/dell/optiplex_9020/sch5555_ec.h |  10 +
+ 7 files changed, 463 insertions(+), 22 deletions(-)
+ create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c
+ create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h
+
+diff --git a/src/mainboard/dell/optiplex_9020/Makefile.mk b/src/mainboard/dell/optiplex_9020/Makefile.mk
+index 6ca2f2afaa..08e2e53577 100644
+--- a/src/mainboard/dell/optiplex_9020/Makefile.mk
++++ b/src/mainboard/dell/optiplex_9020/Makefile.mk
+@@ -2,4 +2,5 @@
+ 
+ romstage-y += gpio.c
+ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+-bootblock-y += bootblock.c
++ramstage-y += sch5555_ec.c
++bootblock-y += bootblock.c sch5555_ec.c
+diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
+index 2837cf9cf1..e5e759273e 100644
+--- a/src/mainboard/dell/optiplex_9020/bootblock.c
++++ b/src/mainboard/dell/optiplex_9020/bootblock.c
+@@ -4,29 +4,14 @@
+ #include <device/pnp_ops.h>
+ #include <superio/smsc/sch555x/sch555x.h>
+ #include <southbridge/intel/lynxpoint/pch.h>
+-
+-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
+-{
+-	// Clear EC-to-Host mailbox
+-	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
+-	outb(tmp, SCH555x_EMI_IOBASE + 1);
+-
+-	// Send address and value to the EC
+-	sch555x_emi_write16(0, (addr1 * 2) | 0x101);
+-	sch555x_emi_write32(4, val | (addr2 << 16));
+-
+-	// Wait for acknowledgement message from EC
+-	outb(1, SCH555x_EMI_IOBASE);
+-	size_t timeout = 0;
+-	do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
+-}
++#include "sch5555_ec.h"
+ 
+ struct ec_init_entry {
+ 	uint16_t addr;
+ 	uint8_t val;
+ };
+ 
+-static void ec_init(void)
++static void bootblock_ec_init(void)
+ {
+ 	/*
+ 	 * Tables from CORE_PEI
+@@ -108,9 +93,9 @@ void mainboard_config_superio(void)
+ 	outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
+ 	outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
+ 
+-	// Magic EC init
+-	ec_init();
++	// Perform bootblock EC initialization
++	bootblock_ec_init();
+ 
+-	// Magic EC init is needed for UART1 initialization to work
++	// Bootblock EC initialization is required for UART1 to work
+ 	sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ }
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
+index a0acd7b6bb..9e02534c16 100644
+--- a/src/mainboard/dell/optiplex_9020/cmos.default
++++ b/src/mainboard/dell/optiplex_9020/cmos.default
+@@ -4,3 +4,4 @@ debug_level=Debug
+ nmi=Disable
+ power_on_after_fail=Disable
+ iommu=Disable
++fan_full_speed=Disable
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
+index 72ff9c4bee..4a1496a878 100644
+--- a/src/mainboard/dell/optiplex_9020/cmos.layout
++++ b/src/mainboard/dell/optiplex_9020/cmos.layout
+@@ -22,7 +22,10 @@ entries
+ 409	2	e	5	power_on_after_fail
+ 
+ # turn iommu on or off
+-412	1	e	6	iommu
++411	1	e	6	iommu
++
++# coreboot config options: EC
++412	1	e	1	fan_full_speed
+ 
+ # coreboot config options: check sums
+ 984	16	h	0	check_sum
+diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
+index c834fea5d3..0b7829c736 100644
+--- a/src/mainboard/dell/optiplex_9020/mainboard.c
++++ b/src/mainboard/dell/optiplex_9020/mainboard.c
+@@ -1,7 +1,12 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+ 
++#include <bootstate.h>
++#include <cpu/x86/msr.h>
+ #include <device/device.h>
+ #include <drivers/intel/gma/int15.h>
++#include <option.h>
++#include <southbridge/intel/common/gpio.h>
++#include "sch5555_ec.h"
+ 
+ static void mainboard_enable(struct device *dev)
+ {
+@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev)
+ struct chip_operations mainboard_ops = {
+ 	.enable_dev = mainboard_enable,
+ };
++
++#define HWM_TAB_ADD_TEMP_TARGET	1
++#define HWM_TAB_PKG_POWER_ANY	0xffff
++#define CHASSIS_TYPE_UNKNOWN	0xff
++
++struct hwm_tab_entry {
++	uint16_t addr;
++	uint8_t val;
++	uint8_t flags;
++	uint16_t pkg_power;
++};
++
++struct hwm_tab_entry HWM_TAB3[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x00, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0x8a, 0, 0x0010 },
++	{ 0x086, 0x4c, 0, 0x0010 },
++	{ 0x08a, 0x66, 0, 0x0010 },
++	{ 0x08b, 0x5b, 0, 0x0010 },
++	{ 0x090, 0x65, 0, 0xffff },
++	{ 0x091, 0x70, 0, 0xffff },
++	{ 0x092, 0x86, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0xa4, 0, 0xffff },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x0e, 0, 0xffff },
++	{ 0x0a1, 0x0e, 0, 0xffff },
++	{ 0x0ae, 0x7c, 0, 0xffff },
++	{ 0x0af, 0x86, 0, 0xffff },
++	{ 0x0b0, 0x9a, 0, 0xffff },
++	{ 0x0b3, 0x9a, 0, 0xffff },
++	{ 0x0b6, 0x08, 0, 0xffff },
++	{ 0x0b7, 0x08, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0x0020 },
++	{ 0x0ea, 0x5c, 0, 0x0010 },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x0fd, 0x01, 0, 0xffff },
++	{ 0x1a1, 0x00, 0, 0xffff },
++	{ 0x1a2, 0x00, 0, 0xffff },
++	{ 0x1b1, 0x08, 0, 0xffff },
++	{ 0x1be, 0x99, 0, 0xffff },
++	{ 0x280, 0xa0, 0, 0x0010 },
++	{ 0x281, 0x0f, 0, 0x0010 },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x288, 0x68, 0, 0x0010 },
++	{ 0x289, 0x10, 0, 0x0010 },
++	{ 0x28a, 0x03, 0, 0xffff },
++	{ 0x28b, 0x0a, 0, 0xffff },
++	{ 0x28c, 0x80, 0, 0xffff },
++	{ 0x28d, 0x03, 0, 0xffff },
++};
++
++struct hwm_tab_entry HWM_TAB4[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x00, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0x99, 0, 0x0020 },
++	{ 0x085, 0xad, 0, 0x0010 },
++	{ 0x086, 0x1c, 0, 0xffff },
++	{ 0x08a, 0x39, 0, 0x0020 },
++	{ 0x08a, 0x41, 0, 0x0010 },
++	{ 0x08b, 0x76, 0, 0x0020 },
++	{ 0x08b, 0x8b, 0, 0x0010 },
++	{ 0x090, 0x5e, 0, 0xffff },
++	{ 0x091, 0x5e, 0, 0xffff },
++	{ 0x092, 0x86, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0xa4, 0, 0xffff },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x0a, 0, 0xffff },
++	{ 0x0a1, 0x0a, 0, 0xffff },
++	{ 0x0ae, 0x7c, 0, 0xffff },
++	{ 0x0af, 0x7c, 0, 0xffff },
++	{ 0x0b0, 0x9a, 0, 0xffff },
++	{ 0x0b3, 0x7c, 0, 0xffff },
++	{ 0x0b6, 0x08, 0, 0xffff },
++	{ 0x0b7, 0x08, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0x0020 },
++	{ 0x0ea, 0x5c, 0, 0x0010 },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x0fd, 0x01, 0, 0xffff },
++	{ 0x1a1, 0x00, 0, 0xffff },
++	{ 0x1a2, 0x00, 0, 0xffff },
++	{ 0x1b1, 0x08, 0, 0xffff },
++	{ 0x1be, 0x90, 0, 0xffff },
++	{ 0x280, 0x94, 0, 0x0020 },
++	{ 0x281, 0x11, 0, 0x0020 },
++	{ 0x280, 0x94, 0, 0x0010 },
++	{ 0x281, 0x11, 0, 0x0010 },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x288, 0x28, 0, 0x0020 },
++	{ 0x289, 0x0a, 0, 0x0020 },
++	{ 0x288, 0x28, 0, 0x0010 },
++	{ 0x289, 0x0a, 0, 0x0010 },
++	{ 0x28a, 0x03, 0, 0xffff },
++	{ 0x28b, 0x0a, 0, 0xffff },
++	{ 0x28c, 0x80, 0, 0xffff },
++	{ 0x28d, 0x03, 0, 0xffff },
++};
++
++struct hwm_tab_entry HWM_TAB5[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x00, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0x66, 0, 0x0020 },
++	{ 0x085, 0x5d, 0, 0x0010 },
++	{ 0x086, 0x1c, 0, 0xffff },
++	{ 0x08a, 0x39, 0, 0x0020 },
++	{ 0x08a, 0x41, 0, 0x0010 },
++	{ 0x08b, 0x76, 0, 0x0020 },
++	{ 0x08b, 0x80, 0, 0x0010 },
++	{ 0x090, 0x5d, 0, 0x0020 },
++	{ 0x090, 0x5e, 0, 0x0010 },
++	{ 0x091, 0x5e, 0, 0xffff },
++	{ 0x092, 0x86, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0xa3, 0, 0x0020 },
++	{ 0x098, 0xa4, 0, 0x0010 },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x08, 0, 0xffff },
++	{ 0x0a1, 0x0a, 0, 0xffff },
++	{ 0x0ae, 0x7c, 0, 0xffff },
++	{ 0x0af, 0x7c, 0, 0xffff },
++	{ 0x0b0, 0x9a, 0, 0xffff },
++	{ 0x0b3, 0x7c, 0, 0xffff },
++	{ 0x0b6, 0x08, 0, 0xffff },
++	{ 0x0b7, 0x08, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0x0020 },
++	{ 0x0ea, 0x5c, 0, 0x0010 },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x0fd, 0x01, 0, 0xffff },
++	{ 0x1a1, 0x00, 0, 0xffff },
++	{ 0x1a2, 0x00, 0, 0xffff },
++	{ 0x1b1, 0x08, 0, 0xffff },
++	{ 0x1be, 0x98, 0, 0x0020 },
++	{ 0x1be, 0x90, 0, 0x0010 },
++	{ 0x280, 0x94, 0, 0x0020 },
++	{ 0x281, 0x11, 0, 0x0020 },
++	{ 0x280, 0x94, 0, 0x0010 },
++	{ 0x281, 0x11, 0, 0x0010 },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x288, 0x28, 0, 0x0020 },
++	{ 0x289, 0x0a, 0, 0x0020 },
++	{ 0x288, 0x28, 0, 0x0010 },
++	{ 0x289, 0x0a, 0, 0x0010 },
++	{ 0x28a, 0x03, 0, 0xffff },
++	{ 0x28b, 0x0a, 0, 0xffff },
++	{ 0x28c, 0x80, 0, 0xffff },
++	{ 0x28d, 0x03, 0, 0xffff },
++};
++
++struct hwm_tab_entry HWM_TAB6[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x00, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0x98, 0, 0xffff },
++	{ 0x086, 0x3c, 0, 0xffff },
++	{ 0x08a, 0x39, 0, 0x0020 },
++	{ 0x08a, 0x3d, 0, 0x0010 },
++	{ 0x08b, 0x44, 0, 0x0020 },
++	{ 0x08b, 0x51, 0, 0x0010 },
++	{ 0x090, 0x61, 0, 0xffff },
++	{ 0x091, 0x6d, 0, 0xffff },
++	{ 0x092, 0x86, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0x9f, 0, 0x0020 },
++	{ 0x098, 0xa4, 0, 0x0010 },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x0e, 0, 0xffff },
++	{ 0x0a1, 0x0e, 0, 0xffff },
++	{ 0x0ae, 0x7c, 0, 0xffff },
++	{ 0x0af, 0x7c, 0, 0xffff },
++	{ 0x0b0, 0x9b, 0, 0x0020 },
++	{ 0x0b0, 0x98, 0, 0x0010 },
++	{ 0x0b3, 0x9a, 0, 0xffff },
++	{ 0x0b6, 0x08, 0, 0xffff },
++	{ 0x0b7, 0x08, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0x0020 },
++	{ 0x0ea, 0x5c, 0, 0x0010 },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x0fd, 0x01, 0, 0xffff },
++	{ 0x1a1, 0x00, 0, 0xffff },
++	{ 0x1a2, 0x00, 0, 0xffff },
++	{ 0x1b1, 0x08, 0, 0xffff },
++	{ 0x1be, 0x9a, 0, 0x0020 },
++	{ 0x1be, 0x96, 0, 0x0010 },
++	{ 0x280, 0x94, 0, 0x0020 },
++	{ 0x281, 0x11, 0, 0x0020 },
++	{ 0x280, 0x94, 0, 0x0010 },
++	{ 0x281, 0x11, 0, 0x0010 },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x288, 0x94, 0, 0x0020 },
++	{ 0x289, 0x11, 0, 0x0020 },
++	{ 0x288, 0x94, 0, 0x0010 },
++	{ 0x289, 0x11, 0, 0x0010 },
++	{ 0x28a, 0x03, 0, 0xffff },
++	{ 0x28b, 0x0a, 0, 0xffff },
++	{ 0x28c, 0x80, 0, 0xffff },
++	{ 0x28d, 0x03, 0, 0xffff },
++};
++
++static uint8_t get_chassis_type(void)
++{
++	uint8_t gpio_chassis_type;
++
++	// Read chassis type from GPIO
++	gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
++			    get_gpio(17) << 1 | get_gpio(1);
++
++	printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
++
++	// Turn it into internal chassis index
++	switch (gpio_chassis_type) {
++	case 0x08:
++	case 0x0a:
++		return 4;
++	case 0x0b:
++		return 3;
++	case 0x0c:
++		return 5;
++	case 0x0d: // SFF
++	case 0x0e:
++	case 0x0f:
++		return 6;
++	default:
++		return CHASSIS_TYPE_UNKNOWN;
++	}
++
++}
++
++static uint8_t get_temp_target(void)
++{
++	uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff;
++	if (!val)
++		val = 20;
++	return 0x95 - val;
++}
++
++static uint16_t get_pkg_power(void)
++{
++	uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf;
++	if (rapl_power_unit)
++		rapl_power_unit = 2 << (rapl_power_unit - 1);
++	uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff;
++	if (pkg_power_info / rapl_power_unit > 0x41)
++		return 32;
++	else
++		return 16;
++}
++
++static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size)
++{
++	uint8_t temp_target = get_temp_target();
++	uint16_t pkg_power = get_pkg_power();
++
++	printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target);
++	printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power);
++
++	for (size_t i = 0; i < size; ++i) {
++		// Skip entry if it doesn't apply for this package power
++		if (arr[i].pkg_power != pkg_power &&
++		    arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY)
++			continue;
++
++		uint8_t val = arr[i].val;
++
++		// Add temp target to value if requested (current tables never do)
++		if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET)
++			val += temp_target;
++
++		// Perform write
++		ec_write(1, arr[i].addr, val);
++
++	}
++}
++
++static void sch5555_ec_hwm_init(void *arg)
++{
++	uint8_t chassis_type, saved_2fc;
++
++	printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n");
++
++	saved_2fc = ec_read(1, 0x2fc);
++	ec_write(1, 0x2fc, 0xa0);
++	ec_write(1, 0x2fd, 0x32);
++
++	chassis_type = get_chassis_type();
++
++	if (chassis_type != CHASSIS_TYPE_UNKNOWN) {
++		printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type);
++	} else {
++		printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n");
++	}
++
++	// Apply HWM table based on chassis type
++	switch (chassis_type) {
++	case 3:
++		apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3));
++		break;
++	case 4:
++		apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4));
++		break;
++	case 5:
++		apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5));
++		break;
++	case 6:
++		apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6));
++		break;
++	}
++
++	// NOTE: vendor firmware applies these when "max core address" > 2
++	// i think this is always the case
++	ec_write(1, 0x9e, 0x30);
++	ec_write(1, 0xeb, ec_read(1, 0xea));
++
++	ec_write(1, 0x2fc, saved_2fc);
++
++	// Apply full speed fan config if requested or if the chassis type is unknown
++	if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) {
++		printk(BIOS_DEBUG, "Setting full fan speed\n");
++		ec_write(1, 0x80, 0x60 | ec_read(1, 0x80));
++		ec_write(1, 0x81, 0x60 | ec_read(1, 0x81));
++	}
++
++	ec_read(1, 0xb8);
++
++	if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) {
++		ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb);
++		ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb);
++		ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb);
++		ec_write(1, 0x8a, 0x99);
++		ec_write(1, 0x8b, 0x47);
++		ec_write(1, 0x8c, 0x91);
++	}
++}
++
++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL);
+diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
+new file mode 100644
+index 0000000000..a1067ac063
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
+@@ -0,0 +1,54 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <arch/io.h>
++#include <device/pnp_ops.h>
++#include <superio/smsc/sch555x/sch555x.h>
++#include "sch5555_ec.h"
++
++uint8_t ec_read(uint8_t addr1, uint16_t addr2)
++{
++	// clear ec-to-host mailbox
++	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
++	outb(tmp, SCH555x_EMI_IOBASE + 1);
++
++	// send address
++	outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
++	outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4);
++
++	outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
++	outl(addr2 << 16, SCH555x_EMI_IOBASE + 4);
++
++	// send message to ec
++	outb(1, SCH555x_EMI_IOBASE);
++
++	// wait for ack
++	for (size_t retry = 0; retry < 0xfff; ++retry)
++		if (inb(SCH555x_EMI_IOBASE + 1) & 1)
++			break;
++
++	// read result
++	outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2);
++	return inb(SCH555x_EMI_IOBASE + 4);
++}
++
++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
++{
++	// clear ec-to-host mailbox
++	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
++	outb(tmp, SCH555x_EMI_IOBASE + 1);
++
++	// send address and value
++	outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
++	outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4);
++
++	outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
++	outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4);
++
++	// send message to ec
++	outb(1, SCH555x_EMI_IOBASE);
++
++	// wait for ack
++	for (size_t retry = 0; retry < 0xfff; ++retry)
++		if (inb(SCH555x_EMI_IOBASE + 1) & 1)
++			break;
++}
+diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
+new file mode 100644
+index 0000000000..7e399e8e74
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
+@@ -0,0 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef __SCH5555_EC_H__
++#define __SCH5555_EC_H__
++
++uint8_t ec_read(uint8_t addr1, uint16_t addr2);
++
++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val);
++
++#endif
+-- 
+2.39.2
+

config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch

@@ -0,0 +1,51 @@
+From ae494dc1b1dde92ec42390b85ced0ffe816f5110 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Sat, 6 Apr 2024 01:22:47 +0100
+Subject: [PATCH 4/4] nb/haswell: Fully disable iGPU when dGPU is used
+
+My earlier patch disabled decode *and* disabled the iGPU itself, but
+a subsequent revision disabled only VGA decode. Upon revisiting, I
+found that, actually, yes, you also need to disable the iGPU entirely.
+
+Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU.
+With this patch, the iGPU is completely disabled when you install a
+graphics card, but the iGPU is available to use when no graphics card
+is present.
+
+For more context, see:
+
+Author: Leah Rowe <info@minifree.org>
+Date:   Fri Feb 23 13:33:31 2024 +0000
+
+    nb/haswell: Disable iGPU when dGPU is used
+
+And look at the Gerrit comments:
+
+https://review.coreboot.org/c/coreboot/+/80717/
+
+So, my original submission on change 80717 was actually correct.
+This patch fixes the issue. I tested on iGPU and dGPU, with both
+broadwell and haswell mrc.bin.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/northbridge/intel/haswell/gma.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
+index 9e9f9804f5..526a51aff0 100644
+--- a/src/northbridge/intel/haswell/gma.c
++++ b/src/northbridge/intel/haswell/gma.c
+@@ -464,6 +464,9 @@ static void gma_func0_disable(struct device *dev)
+ {
+ 	/* Disable VGA decode */
+ 	pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
++
++	/* Required or else the graphics card doesn't work */
++	dev->enabled = 0;
+ }
+ 
+ static struct device_operations gma_func0_ops = {
+-- 
+2.39.2
+

config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch

@@ -0,0 +1,49 @@
+From 355536155898e649fa50277136ccd2df53a52bb1 Mon Sep 17 00:00:00 2001
+From: Mate Kukri <kukri.mate@gmail.com>
+Date: Wed, 10 Apr 2024 20:31:35 +0100
+Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device
+
+These machines come with a TPM1.2 device by default. It is somewhat
+obsolete these days, but there is no harm in enabling it.
+
+Change-Id: Iec05321862aed58695c256b00494e5953219786d
+Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827
+Reviewed-by: Angel Pons <th3fanbus@gmail.com>
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+---
+ src/mainboard/dell/optiplex_9020/Kconfig       | 2 ++
+ src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
+index 2de4a9abd6..38c3281e70 100644
+--- a/src/mainboard/dell/optiplex_9020/Kconfig
++++ b/src/mainboard/dell/optiplex_9020/Kconfig
+@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select INTEL_GMA_HAVE_VBT
+ 	select INTEL_INT15
+ 	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_HAS_TPM1
+ 	select MAINBOARD_USES_IFD_GBE_REGION
++	select MEMORY_MAPPED_TPM
+ 	select NORTHBRIDGE_INTEL_HASWELL
+ 	select SERIRQ_CONTINUOUS_MODE
+ 	select SOUTHBRIDGE_INTEL_LYNXPOINT
+diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
+index dce5869478..841285bb9c 100644
+--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
+@@ -70,6 +70,9 @@ chip northbridge/intel/haswell
+ 					device pnp 2e.b  off end	# Floppy Controller
+ 					device pnp 2e.11 off end	# Parallel Port
+ 				end
++				chip drivers/pc80/tpm
++					device pnp 0c31.0 on end
++				end
+ 			end
+ 			device pci 1f.2 on  end				# SATA controller 1
+ 			device pci 1f.3 on  end				# SMBus
+-- 
+2.39.2
+

config/coreboot/haswell/target.cfg

@@ -0,0 +1,3 @@
+tree="haswell"
+rev="b7341da19133991efd29880849bdaab29a6e243d"
+xarch="i386-elf"

config/coreboot/hp820g2_12mb/target.cfg

@@ -5,3 +5,4 @@ payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
 grub_scan_disk="ahci"
+release="n"

config/coreboot/t440pbmrc_12mb/target.cfg

@@ -5,3 +5,4 @@ payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
 grub_scan_disk="ahci"
+release="n"

config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb

@@ -6,7 +6,6 @@
 #
 # General setup
 #
-CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -113,28 +112,29 @@ CONFIG_VGA_BIOS_ID="8086,0416"
 CONFIG_DIMM_MAX=4
 CONFIG_DIMM_SPD_SIZE=256
 CONFIG_FMDFILE=""
-CONFIG_NO_POST=y
+# CONFIG_NO_POST is not set
 CONFIG_MAINBOARD_VENDOR="LENOVO"
 CONFIG_CBFS_SIZE=0x800000
 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
 CONFIG_MAX_CPUS=8
 CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
 CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
 # CONFIG_VBOOT is not set
 CONFIG_VARIANT_DIR="t440p"
 CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_USBDEBUG_HCD_INDEX=2
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
 CONFIG_TPM_PIRQ=0x0
-CONFIG_PS2K_EISAID="LEN0071"
-CONFIG_PS2M_EISAID="LEN0036"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -163,6 +163,7 @@ CONFIG_HAVE_IFD_BIN=y
 CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
 # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set
 # CONFIG_BOARD_LENOVO_L520 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set
 # CONFIG_BOARD_LENOVO_S230U is not set
 # CONFIG_BOARD_LENOVO_T400 is not set
 # CONFIG_BOARD_LENOVO_T500 is not set
@@ -183,6 +184,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
 # CONFIG_BOARD_LENOVO_Z61T is not set
 # CONFIG_BOARD_LENOVO_R60 is not set
 # CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set
 # CONFIG_BOARD_LENOVO_X131E is not set
 # CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set
 # CONFIG_BOARD_LENOVO_X200 is not set
@@ -191,7 +193,6 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
 # CONFIG_BOARD_LENOVO_X220 is not set
 # CONFIG_BOARD_LENOVO_X220I is not set
 # CONFIG_BOARD_LENOVO_X1 is not set
-# CONFIG_BOARD_LENOVO_X220_EDP is not set
 # CONFIG_BOARD_LENOVO_X230 is not set
 # CONFIG_BOARD_LENOVO_X230T is not set
 # CONFIG_BOARD_LENOVO_X230S is not set
@@ -199,6 +200,8 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
 # CONFIG_BOARD_LENOVO_X60 is not set
 CONFIG_BOARD_LENOVO_HASWELL_COMMON=y
 CONFIG_VBOOT_SLOTS_RW_AB=y
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN0036"
 CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
 CONFIG_D3COLD_SUPPORT=y
@@ -208,6 +211,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -253,6 +257,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xe8000000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -262,7 +267,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
@@ -359,6 +363,7 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
 CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
+CONFIG_H8_HAS_LEDLOGO=y
 CONFIG_EC_LENOVO_PMH7=y
 
 #
@@ -435,7 +440,7 @@ CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
 CONFIG_USE_DDR3=y
 # end of Devices
 
@@ -490,12 +495,13 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
-CONFIG_USE_PC_CMOS_ALTCENTURY=y
+# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_MEMORY_MAPPED_TPM=y
 CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
+CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -557,7 +563,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -573,18 +578,23 @@ CONFIG_CONSOLE_CBMEM=y
 # CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_EM100PRO_SPI_CONSOLE is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
 CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-CONFIG_HWBASE_DEBUG_NULL=y
+# CONFIG_CMOS_POST is not set
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO_PORT=0x80
+CONFIG_HWBASE_DEBUG_CB=y
 # end of Console
 
 CONFIG_HAVE_ACPI_RESUME=y
@@ -634,6 +644,7 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_MALLOC is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set

config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode

@@ -6,7 +6,6 @@
 #
 # General setup
 #
-CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -113,26 +112,27 @@ CONFIG_VGA_BIOS_ID="8086,0416"
 CONFIG_DIMM_MAX=4
 CONFIG_DIMM_SPD_SIZE=256
 CONFIG_FMDFILE=""
-CONFIG_NO_POST=y
+# CONFIG_NO_POST is not set
 CONFIG_MAINBOARD_VENDOR="LENOVO"
 CONFIG_CBFS_SIZE=0x800000
 CONFIG_MAX_CPUS=8
 CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
 CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
 # CONFIG_VBOOT is not set
 CONFIG_VARIANT_DIR="t440p"
 CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_USBDEBUG_HCD_INDEX=2
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
 CONFIG_TPM_PIRQ=0x0
-CONFIG_PS2K_EISAID="LEN0071"
-CONFIG_PS2M_EISAID="LEN0036"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -161,6 +161,7 @@ CONFIG_HAVE_IFD_BIN=y
 CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
 # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set
 # CONFIG_BOARD_LENOVO_L520 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set
 # CONFIG_BOARD_LENOVO_S230U is not set
 # CONFIG_BOARD_LENOVO_T400 is not set
 # CONFIG_BOARD_LENOVO_T500 is not set
@@ -181,6 +182,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
 # CONFIG_BOARD_LENOVO_Z61T is not set
 # CONFIG_BOARD_LENOVO_R60 is not set
 # CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set
 # CONFIG_BOARD_LENOVO_X131E is not set
 # CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set
 # CONFIG_BOARD_LENOVO_X200 is not set
@@ -189,7 +191,6 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
 # CONFIG_BOARD_LENOVO_X220 is not set
 # CONFIG_BOARD_LENOVO_X220I is not set
 # CONFIG_BOARD_LENOVO_X1 is not set
-# CONFIG_BOARD_LENOVO_X220_EDP is not set
 # CONFIG_BOARD_LENOVO_X230 is not set
 # CONFIG_BOARD_LENOVO_X230T is not set
 # CONFIG_BOARD_LENOVO_X230S is not set
@@ -197,6 +198,8 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y
 # CONFIG_BOARD_LENOVO_X60 is not set
 CONFIG_BOARD_LENOVO_HASWELL_COMMON=y
 CONFIG_VBOOT_SLOTS_RW_AB=y
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN0036"
 CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
 CONFIG_D3COLD_SUPPORT=y
@@ -206,6 +209,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -251,6 +255,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xe8000000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -260,7 +265,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
@@ -357,6 +361,7 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
 CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
+CONFIG_H8_HAS_LEDLOGO=y
 CONFIG_EC_LENOVO_PMH7=y
 
 #
@@ -431,7 +436,7 @@ CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
 CONFIG_USE_DDR3=y
 # end of Devices
 
@@ -486,13 +491,14 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
-CONFIG_USE_PC_CMOS_ALTCENTURY=y
+# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_MEMORY_MAPPED_TPM=y
 CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
+CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -554,7 +560,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -570,18 +575,23 @@ CONFIG_CONSOLE_CBMEM=y
 # CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_EM100PRO_SPI_CONSOLE is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
 CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-CONFIG_HWBASE_DEBUG_NULL=y
+# CONFIG_CMOS_POST is not set
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO_PORT=0x80
+CONFIG_HWBASE_DEBUG_CB=y
 # end of Console
 
 CONFIG_HAVE_ACPI_RESUME=y
@@ -631,6 +641,7 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_MALLOC is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set

config/coreboot/t440plibremrc_12mb/target.cfg

@@ -1,4 +1,4 @@
-tree="default"
+tree="haswell"
 xarch="i386-elf"
 payload_grub="y"
 payload_grub_withseabios="y"

config/coreboot/t440pmrc_12mb/target.cfg

@@ -5,3 +5,4 @@ payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
 grub_scan_disk="ahci"
+release="n"

config/coreboot/w541_12mb/config/libgfxinit_corebootfb

@@ -6,7 +6,6 @@
 #
 # General setup
 #
-CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -113,28 +112,29 @@ CONFIG_VGA_BIOS_ID="8086,0166"
 CONFIG_DIMM_MAX=4
 CONFIG_DIMM_SPD_SIZE=256
 CONFIG_FMDFILE=""
-CONFIG_NO_POST=y
+# CONFIG_NO_POST is not set
 CONFIG_MAINBOARD_VENDOR="LENOVO"
 CONFIG_CBFS_SIZE=0x800000
 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
 CONFIG_MAX_CPUS=8
 CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
 CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
 # CONFIG_VBOOT is not set
 CONFIG_VARIANT_DIR="w541"
 CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_USBDEBUG_HCD_INDEX=2
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
 CONFIG_TPM_PIRQ=0x0
-CONFIG_PS2K_EISAID="LEN0071"
-CONFIG_PS2M_EISAID="LEN004A"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -163,6 +163,7 @@ CONFIG_HAVE_IFD_BIN=y
 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set
 CONFIG_BOARD_LENOVO_THINKPAD_W541=y
 # CONFIG_BOARD_LENOVO_L520 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set
 # CONFIG_BOARD_LENOVO_S230U is not set
 # CONFIG_BOARD_LENOVO_T400 is not set
 # CONFIG_BOARD_LENOVO_T500 is not set
@@ -183,6 +184,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y
 # CONFIG_BOARD_LENOVO_Z61T is not set
 # CONFIG_BOARD_LENOVO_R60 is not set
 # CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set
 # CONFIG_BOARD_LENOVO_X131E is not set
 # CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set
 # CONFIG_BOARD_LENOVO_X200 is not set
@@ -191,7 +193,6 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y
 # CONFIG_BOARD_LENOVO_X220 is not set
 # CONFIG_BOARD_LENOVO_X220I is not set
 # CONFIG_BOARD_LENOVO_X1 is not set
-# CONFIG_BOARD_LENOVO_X220_EDP is not set
 # CONFIG_BOARD_LENOVO_X230 is not set
 # CONFIG_BOARD_LENOVO_X230T is not set
 # CONFIG_BOARD_LENOVO_X230S is not set
@@ -199,6 +200,8 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y
 # CONFIG_BOARD_LENOVO_X60 is not set
 CONFIG_BOARD_LENOVO_HASWELL_COMMON=y
 CONFIG_VBOOT_SLOTS_RW_AB=y
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN004A"
 CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"
 CONFIG_GFX_GMA_PANEL_1_PORT="DP3"
 CONFIG_D3COLD_SUPPORT=y
@@ -208,6 +211,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -253,6 +257,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xe8000000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -262,7 +267,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
@@ -359,6 +363,7 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
 CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
+CONFIG_H8_HAS_LEDLOGO=y
 CONFIG_EC_LENOVO_PMH7=y
 
 #
@@ -435,7 +440,7 @@ CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
 CONFIG_USE_DDR3=y
 # end of Devices
 
@@ -489,12 +494,13 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
-CONFIG_USE_PC_CMOS_ALTCENTURY=y
+# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_MEMORY_MAPPED_TPM=y
 CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
+CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -556,7 +562,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -583,6 +588,11 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
 CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
+# CONFIG_CMOS_POST is not set
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO_PORT=0x80
 CONFIG_HWBASE_DEBUG_CB=y
 # end of Console
 

config/coreboot/w541_12mb/config/libgfxinit_txtmode

@@ -6,7 +6,6 @@
 #
 # General setup
 #
-CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -113,26 +112,27 @@ CONFIG_VGA_BIOS_ID="8086,0166"
 CONFIG_DIMM_MAX=4
 CONFIG_DIMM_SPD_SIZE=256
 CONFIG_FMDFILE=""
-CONFIG_NO_POST=y
+# CONFIG_NO_POST is not set
 CONFIG_MAINBOARD_VENDOR="LENOVO"
 CONFIG_CBFS_SIZE=0x800000
 CONFIG_MAX_CPUS=8
 CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
 CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
 # CONFIG_VBOOT is not set
 CONFIG_VARIANT_DIR="w541"
 CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_USBDEBUG_HCD_INDEX=2
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
 CONFIG_TPM_PIRQ=0x0
-CONFIG_PS2K_EISAID="LEN0071"
-CONFIG_PS2M_EISAID="LEN004A"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -161,6 +161,7 @@ CONFIG_HAVE_IFD_BIN=y
 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set
 CONFIG_BOARD_LENOVO_THINKPAD_W541=y
 # CONFIG_BOARD_LENOVO_L520 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set
 # CONFIG_BOARD_LENOVO_S230U is not set
 # CONFIG_BOARD_LENOVO_T400 is not set
 # CONFIG_BOARD_LENOVO_T500 is not set
@@ -181,6 +182,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y
 # CONFIG_BOARD_LENOVO_Z61T is not set
 # CONFIG_BOARD_LENOVO_R60 is not set
 # CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set
 # CONFIG_BOARD_LENOVO_X131E is not set
 # CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set
 # CONFIG_BOARD_LENOVO_X200 is not set
@@ -189,7 +191,6 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y
 # CONFIG_BOARD_LENOVO_X220 is not set
 # CONFIG_BOARD_LENOVO_X220I is not set
 # CONFIG_BOARD_LENOVO_X1 is not set
-# CONFIG_BOARD_LENOVO_X220_EDP is not set
 # CONFIG_BOARD_LENOVO_X230 is not set
 # CONFIG_BOARD_LENOVO_X230T is not set
 # CONFIG_BOARD_LENOVO_X230S is not set
@@ -197,6 +198,8 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y
 # CONFIG_BOARD_LENOVO_X60 is not set
 CONFIG_BOARD_LENOVO_HASWELL_COMMON=y
 CONFIG_VBOOT_SLOTS_RW_AB=y
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN004A"
 CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"
 CONFIG_GFX_GMA_PANEL_1_PORT="DP3"
 CONFIG_D3COLD_SUPPORT=y
@@ -206,6 +209,7 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -251,6 +255,7 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xe8000000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -260,7 +265,6 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
@@ -357,6 +361,7 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
 CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
+CONFIG_H8_HAS_LEDLOGO=y
 CONFIG_EC_LENOVO_PMH7=y
 
 #
@@ -431,7 +436,7 @@ CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
 CONFIG_USE_DDR3=y
 # end of Devices
 
@@ -485,13 +490,14 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
-CONFIG_USE_PC_CMOS_ALTCENTURY=y
+# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_MEMORY_MAPPED_TPM=y
 CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
+CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -553,7 +559,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -580,6 +585,11 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
 CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
+# CONFIG_CMOS_POST is not set
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO_PORT=0x80
 CONFIG_HWBASE_DEBUG_CB=y
 # end of Console
 

config/coreboot/w541_12mb/target.cfg

@@ -1,4 +1,4 @@
-tree="default"
+tree="haswell"
 xarch="i386-elf"
 payload_grub="y"
 payload_grub_withseabios="y"

config/coreboot/w541bmrc_12mb/target.cfg

@@ -5,3 +5,4 @@ payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
 grub_scan_disk="ahci"
+release="n"

config/coreboot/w541mrc_12mb/target.cfg

@@ -5,3 +5,4 @@ payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
 grub_scan_disk="ahci"
+release="n"

config/vendor/sources

@@ -35,7 +35,7 @@
 
 # NOTE: google's manifest for archives containing mrc.bin, used here:
 # https://web.archive.org/web/20210211071412/https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf
-{t440pmrc w541mrc t440plibremrc w541 dell9020mt-nri dell9020mt dell9020sff-nri dell9020sff}{
+{t440pmrc w541mrc t440plibremrc w541 dell9020mt dell9020sff dell9020sff-nri dell9020mt-nri}{
 	DL_hash f3d79aec805c8b0094a4081be76b3a22d329c479ad18210449b7acc3236ccfc4a2103eaa7c5b79a4872bfd699eede047efd46dfb06dc8f47e3216fc254612998
 	DL_url https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe
 	DL_url_bkup https://web.archive.org/web/20211120031520/https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe

include/err.sh

@@ -2,7 +2,28 @@
 # SPDX-FileCopyrightText: 2022, 2023 Leah Rowe <leah@libreboot.org>
 
 version=""; versiondate=""; projectname=""; _nogit=""
-err="err_"
+err="err_"; tmpdir=""
+
+# if "y": a coreboot target won't be built if target.cfg says release="n"
+# (this is used to exclude certain build targets from releases)
+lbmk_release=
+set | grep LBMK_RELEASE 1>/dev/null 2>/dev/null || lbmk_release="n" || :
+[ -z "$lbmk_release" ] && lbmk_release="$LBMK_RELEASE"
+[ "$lbmk_release" = "n" ] || [ "$lbmk_release" = "y" ] || lbmk_release="n"
+
+tmpdir_was_set="y"
+set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n"
+if [ "${tmpdir_was_set}" = "y" ]; then
+	[ "${TMPDIR%_*}" = "/tmp/lbmk" ] || tmpdir_was_set="n"
+fi
+if [ "${tmpdir_was_set}" = "n" ]; then
+	export TMPDIR="/tmp"
+	tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)"
+	export TMPDIR="${tmpdir}"
+else
+	export TMPDIR="${TMPDIR}"
+	tmpdir="${TMPDIR}"
+fi
 
 x_() {
 	[ $# -lt 1 ] || ${@} || $err "Unhandled non-zero exit: $@"; return 0

script/build/roms

@@ -20,7 +20,7 @@ cfgsdir="config/coreboot"
 # target.cfg files have to specifically enable [a] payload(s)
 pv="payload_grub payload_grub_withseabios payload_seabios payload_memtest t"
 pv="${pv} payload_seabios_withgrub payload_seabios_grubonly payload_uboot memtest_bin"
-v="romdir cbrom initmode displaymode cbcfg targetdir tree keymaps"
+v="romdir cbrom initmode displaymode cbcfg targetdir tree keymaps release"
 v="${v} grub_timeout ubdir board grub_scan_disk uboot_config"
 eval "$(setvars "n" ${pv})"
 eval "$(setvars "" ${v} boards _displaymode _payload _keyboard all targets)"
@@ -56,6 +56,13 @@ main()
 		grub_background="background1280x800.png"
 		board="${x}"
 		configure_target
+
+		# exclude certain targets from the release
+		if [ "$release" = "n" ] && [ "$lbmk_release" = "y" ]; then
+			printf "Skipping target: %s\n" "$x"
+			continue
+		fi
+
 		build_payloads
 		build_target_mainboard
 		[ -d "bin/${board}" ] || continue
@@ -194,7 +201,8 @@ build_target_mainboard()
 			    [ "$displaymode" != "txtmode" ] && continue
 			cbcfg="${targetdir}/config/${initmode}_${displaymode}"
 			[ "${initmode}" = "normal" ] && cbcfg="${cbcfg%_*}"
-			build_roms "${cbcfg}"	
+			build_roms "${cbcfg}"
+			x_ rm -f "$cbrom"
 		done
 	done
 }

script/update/release

@@ -9,6 +9,8 @@ set -u -e
 
 eval "$(setvars "" vdir relname src_dirname srcdir _xm target romdir mode)"
 
+export LBMK_RELEASE="y"
+
 main()
 {
 	vdir="release"